In this paper, a brief overview of TID effect in SOI technology is presented. The introduction of buried oxide(BOX) adds vulnerability to TID effect in SOI transistors because of its large thickness. Also the BOX introduces special charge traps, the delocalized spin centers, which in most cases are positive. The charge buildup in BOX could increase the leakage current in front gate transistor i...

Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.

For SOI nMOSFET, the impact of high tensile stress contact etch stop layer (CESL) on device performance and reliability was investigated. In this work, device driving capability can be enhanced with thicker CESL, larger LOD and narrower gate width. With electrical and body potential inspection, serious device’s degradation happened on SOI-MOSFET with narrow gate device because of STI-induced ed...

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parame...

− This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pnjunction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and νMOS circuits. Index Terms −SOI, gated-pn junction, neural logic,

−Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed. Index Terms−Reli...

Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% co...

The concept of matched devices is one of the most important features in analog circuit design, as most analog circuits operation rely on the similarity of electrical behavior of close devices [1]. However, in practice, the characteristics of designed matched transistors are slightly different. Therefore, the design of precise analog circuits requires studies into the matching behavior of device...

Optical data communication is not the only area where silicon photonics will have an impact. Silicon and related group 4 crystals have excellent linear and nonlinear optical properties in the midwave and longwave infrared spectrum [1-6]. These properties, along with silicon’s excellent thermal conductivity and optical damage threshold, open up the possibility for a new class of midwave and long...