Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, energy-efficient switching activity techniques have applied with propos...

Investments in process technologies during the past two decades to increase productivity and efficiency in product development have not yielded the gains in productivity that would be expected. This lack of return on investment is due to injecting new process technologies and tools into old product development processes. Globalization and mass customization, termed 'the new business imperative'...

Carbon Nanotube FETs (CNFETs) are showing significant promise in nanoelectronics. They are one of the principle areas of research that are seen as having the capability of replacing MOSFET transistors. In fact, their performance is much better than MOSFETs below 10nm [1], with the operation frequencies of CNFET devices being up to1000 times greater. This project investigates various properties ...

With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. As the size of chips is shrinking and the density is increasing simultaneously, losses are increasing mostly in the form of power dissipation. Based on various parameters of performance evaluation in a VLSI circu...

this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit f...

The steady reduction in the dimension of transistors, according to Moore's law has been the main force behind the regular leaps in the level of performance of the silicon ICs. Due to the effects like the short channel effects, tunnelling effect, additional heat dissipation, interconnect problems etc problems arise. So it is not possible to reduce the size further. Hence now it is necessary to a...

This paper describes a transistor sizing methodology for both analog and digital CMOS circuits. Various techniques are used for power optimization in CMOS VLSI circuits. Transistor sizing is one of the important techniques for the determination of circuit performance. The aim of the power optimization is to minimize the power and power-delay product or the energy consumption of the circuit. Thu...

SRAM is a semiconductor memory cell. In this paper, a 10T SRAM cell is designed by using cadence virtuoso tool in 180nm CMOS technology. Its performance characteristics such as power, delay, and power delay product are analysed. 10T SRAM cell is basically 6T SRAM cell with 4 extra transistors. In this 10T SRAM cell, additional read circuitry is attached to avoid flipping of cell. The power diss...