A chip has been designed and tested to demonstrate the feasibility of an ultra-low-power, two-dimensional inverse discrete cosine transform (IDCT) computation unit in a standard 3.3-V process. A data-driven computation algorithm that exploits the relative occurrence of zero-valued DCT coefficients coupled with clock gating has been used to minimize switched capacitance. In addition, circuit and...

In this paper we present low-power 77-GHz power amplifier (PA) for the long range automotive radar. The proposed amplifier is designed using TSMC 0.13-μm RF CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5V supply. To reduce power dissipation, we consider bias voltage, transistor size optimization, matchings and layout optimization. To improve power gain of the amplifier, it ha...

In this paper, we investigate the degree to which power dissipation induced by program execution can be measured by application-level software tools and predicted by a compiler and runtime system. Application control of the power it uses while executing on a processor is critical to battery-powered mobile devices that are an integral to any realization of ubiquitous computing. Our work investig...

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.

Portable devices demand for low power dissipation. To reduce power dissipation, the subsystem in a device needs to be designed to operate at low power and also consume low power. Significant progress has been made in low power design of dynamic RAM’s. Static RAM’s are also critical in most VLSI based system on chip applications. Basic SRAM bit cell consists of 6T. Few designs using 4T are also ...

This paper addresses power consumption in CMOS logic gates through an study considering the design and technology points-of-view. Through SPICE simulations, the relationship between charge/discharge and short-circuit components of dynamic power consumption are investigated both considering different logic gates and its evolution through technology scaling. Experimental results show that dynamic...

In this paper, we address the problem of state assignment to minimise both area and power dissipation for Finite State Machine designs. We propose a new matching-based state-assignment algorithm which considers area and state transitions simultiG neously. Experimental results on a set of benchmarks demonstrate that our approach is indeed very effective in minimising both area and power dissipat...

This paper introduces an architecture for quantumdot cellular automata (QCA) systems with the potential for high throughput and low power dissipation. The combination of regions with Bennett clocking and of regions used for memory storage combines the low power advantages of reversible computing and the high throughput advantages of pipelining. A simple case study is employed to evaluate the pr...

Two cases of power dissipation reduction with postfabrication adjustment using genetic algorithms are introduced in this paper. The first is a 1GHz ALU implementation, where power consumption has been reduced by 54% through clock-timing adjustment. The second case is the IF (Intermediate Frequency) filter analog LSI used in cellular phones, where the reduction in power dissipation is realized b...

The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits ...