According to the demand on enormous multimedia data processing, we have designed a VLIW (Very Long Instruction Word) processor called DIVA(Dual-Issue VLIW Architecture) exploiting the ILP(instruction-level parallelism) in multimedia programs. DIVA processor which can execute two instructions in one cycle supports 86 instructions including 30 media instructions, and has a sub-word execution stru...

Preschool-age children (N=58) were randomly assigned to receive instruction in letter names and sounds, letter sounds only, or numbers (control). Multilevel modeling was used to examine letter name and sound learning as a function of instructional condition and characteristics of both letters and children. Specifically, learning was examined in light of letter name structure, whether letter nam...

This paper presents an instruction scheduling algorithm based on the Subgraph Isomorphism Problem. Given a Directed Acyclic Graph (DAG) G1, our algorithm looks for a subgraph G2 in a base graph G2, such that G ′ 2 is isomorphic to G1. The base graph G2 represents the arrangement of the processing elements of a high performance computer architecture named 2D-VLIW and G2 is the set of those proce...

Fine-grained linear processor arrays are an important class of architectures for obtaining high performance on computationally intensive algorithms with large data sets, as found prevalently in digital signal processing and scientiic computing. The vast number of processing elements on these architectures provides a immense amount of potential parallelism but at the price of limited interconnec...

High performance processors based on pipeline processing play an important role in scientific computation. We have proposed a hybrid pipeline architecture named Jetpipeline in our former work. The concept of Jetpipeline comes from the integration of superscalar, VLIW and vector architectures. Jetpipeline has multiple instruction pipelines, which execute multiple instructions like superscalar ar...

Process dissociation is based on 2 assumptions about the processes being dissociated: invariance of the processes across situations, and stochastic independence of the processes. In a recent application of process dissociation to the Stroop task (D. S. Lindsay & L. L. Jacoby, 1994), both of those assumptions were violated. It is argued that these violations were due to (a) an oversimplification...

0272-1732/00/$10.00  2000 IEEE Because conventional RISC processors have insufficient processing power to support the continuing development of digital consumer products, we need a new highperformance processor for multimedia applications. Processing multimedia video images requires more than 10 times the currently available performance. At Fujitsu, we provide this higher performance in softwa...

Modern network interfaces demand highly intelligent traffic management in addition to the basic requirement of wire speed packet forwarding. Several vendors are releasing network processors in order to handle these demands. Network workloads can be classified into data plane and control plane workloads, however most network processors are optimized for data plane. Also, existing benchmark suite...

Processor Martin T. Rowland and Randall A. Helzerman Intel Corporation, Design Technologies 2111 N.E. 25th Avenue JF1-71 Hillsboro, OR 97124-5961 August 23, 1995 Abstract Because dependencies limit the amount of parallelism in an instruction stream, a VLIW or superscalar processor typically cannot execute as many instructions each cycle as it has functional units. This otherwise wasted processi...

In this paper, we describe application-specific extensions for fuzzy processing to a general purpose processor. The application-specific instruction set extensions were defined and evaluated using hardware/software codesign techniques. Based on this approach, we have extended the MIPS instruction set architecture with only a few new instructions to significantly speed up fuzzy computation with ...