This paper presents the implementation of the compiler technique register pipelining with respect to energy optimization and its comparison against performance optimization. Generally, programs optimized for performance are also energy optimized. An exception to this rule is shown where the use of register pipelining improves the energy consumption by 17% while bringing down performance by 8.8%...

POPS ts a processor for a simple nondeterminist ic programming language, PSL. POPS accepts a problem stated in PSL and attempts to solve it by f inding a successfu l execut ion of the PSL program, POPS operates by ident i fy ing elements of the input program wi th elements of the heur is t ic search paradigm, analyzing the input program to obta in informat ion about the problem operat o r s , a...

This paper discusses an approach to reducing mem ory latency in future systems It focuses on systems where a single chip DRAM processor will not be fea sible even in years e g systems requiring a large memory and or many CPU s In such systems a solu tion needs to be found to DRAM latency and bandwidth as well as to inter chip communication Utilizing the projected advances in chip I O bandwidth ...

In this paper we present a run-time mechanism to simultaneously execute multiple threads from a sequential program on a simultaneous multithreaded (SMT) processor. The threads are speculative in the sense that they are created by predicting the future control flow of the program. Moreover, threads are not necessarily independent. Data dependences among simultaneously executed threads may exist....

The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores are here today, the future is likely to witness architectures that use reconfigurable fabrics (FPGAs) as coprocessors. FPGAs provide an unmatched ability to tailor their circuitry per application, leading to better performance at...

As the amount of on-chip cache increases as a result of Moore’s law, cache utilization is increasingly important as the number of processor cores multiply and the contention for memory bandwidth becomes more severe. Optimal cache management requires knowing the future access sequence and being able to communicate this information to hardware. The paper addresses the communication problem with t...

Recent advances in network technology promise to make gigabit-per-second bandwidth between remote hosts a reality in the near future. This increase in bandwidth paves the way for increased exploitation of distributed computing resources. Coupled with advances in distributed memory parallel compiler technology, there is strong reason to believe that wide-area distributed parallel processing will...

CollabCAD is an indigenous 3D CAD/CAM software system for collaborative design and development of Industrial Designs for strategic use. This work is for CAM module of the indigenous software, in which the development of post-processor is the task that is accomplished. The CAD model is created in CollabCAD and the required tool path was produced in a generic format known as Cutter Location (CL) ...

Post-silicon validation has always been an integral and crucial phase of microprocessor design and manufacturing process. As technology shrinks and processor becomes more complex, the difficulty has significantly increased in validation for multi-core micro-processor. Ilya Wangner and Valeria Bertacco proposed Reversi, a post-silicon validation system for single core microprocessor in 2008, whi...

An important and recurring security scenario involves the need to carry out trusted computations in the context of untrusted environments. It is shown how a tamper-resistant interpreter for a programming language – currently Lisp 1.5 – combined with the use of a secure co-processor can address this problem. This solution executes the interpreter on the secure coprocessor while the code and data...