A JFET-based circuit for realizing a precision and linear floating voltage-controlled resistance (VCR) is presented for use in analog multipliers and programmable analog circuits and as a resistance mirror. It uses a matched JFET pair along with an op amp based negative feedback for realizing a precision resistance and a feedback of the source and drain voltages to the gate for realizing a line...

An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabilities are propagated and normalized u...

As FPGA densities have increased, the feasibility of using floatingpoint computations on FPGAs has improved. Moreover, recent innovations in FPGA architecture have changed the design tradeoff space by providing new fixed circuit functions which may be employed in floating-point computations. These include high density multiplier blocks and shift registers. This paper evaluates the use of such b...

Introduction Implementation of floating point in FPGA (Field Programmable Gate Arrays) is not easy. Paper presents FPGA core implementing these operations by representation of floating point numbers as 32-bit integer (fixed point) logarithm [1]. Basic arithmetical operations are performed in the logarithm numbering system (LNS) suitable for FPGA. Implemented intellectual property core takes jus...

We have studied how the solution of partial differential equations by means of finite element methods could be accelerated using Field Programmable Gate Arrays (FPGAs). First, we discuss in general the capabilities of current FPGA technology for floating-point implementations of number crunching. Based on practical results for basic floating-point operators performance limits are outlined. Then...

Vdd Vdd Vdd A floating-gate pseudo-differential transconductor is presented, in which the differential input signal is allowed to have a dc offset. Normally such an offset would render a normal CMOS differential pair useless. The circuit "VX v y " inherently removes any dc offset from the floating gates lout(-) lO"I(+) by feedback mechanisms involving Fowler-Nordheim electron tunneling and hot-...

Experimental results from GaN-based high electron mobility transistors (HEMTs) show a pronounced decrease of the transconductance gm at higher gate bias, due to increasing source-gate and gate-drain resistances. In this work we show through simulations that the electric field distribution and the resulting carrier velocity quasi-saturation are the main source for the transconductance collapse, ...

in this paper, a low voltage and low power (lv/lp) operational transconductance amplifier (ota) using fgmos (floating-gate mos) transistor is proposed. the relative tuning range of 50 is achieved in this ota while only consumes 40 µw with 1.0 v supply voltage in tsmc 0.18 µm cmos technology. the simulation results of the proposed ota show an open loop gain of 30.2 db and a unity gain frequency ...