نتایج جستجو برای: reconfigurable instruction set processor

تعداد نتایج: 740389  

1998
Jin-Hyuk Yang Byoung-Woon Kim Sang-Jun Nam Jang-Ho Cho Sung-Won Seo Chang-Ho Ryu Young-Su Kwon Dae-Hyun Lee Jong-Yeol Lee Jong-Sun Kim Hyun-Dhong Yoon Jae-Yeol Kim Kun-Moo Lee Chan-Soo Hwang In-Hyung Kim Jun-Sung Kim Kwang-Il Park Kyu-Ho Park Yong-Hoon Lee Seung-Ho Hwang In-Cheol Park Chong-Min Kyung

This paper describes the MetaCore system which is an ASIP(Application-Speci c Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to o er an e cient design methodology meeting speci cations given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and des...

2015

A complex instruc7on set computer is a computer where single instruc7ons can execute several obscure BiT oriented instruction sets, RISC Instructions Superscalar processors of the 1990s had the func7onal units to execute mul7ple. Preface This book emerged from the course Superscalar Processor Design, which has While the instruction count may go down M O D E R N PROCESSOR Significant effort has ...

2005
Georgi Kuzmanov Georgi Gaydadjiev Stamatis Vassiliadis

We present a fully operational prototype of the Molen reconfigurable processor based on the tightly coupled co-processor architectural paradigm. Within the Molen concept, a general purpose core processor controls the execution and reconfiguration of a reconfigurable co-processor, tuning the latter to various application specific algorithms. An ISA extension of only 4 instructions supports an ar...

2003
Sven Beyer Christian Jacobi Daniel Kroening Dirk Leinenbach Wolfgang J. Paul

In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried ...

2003
Attila Egri-Nagy Chrystopher L. Nehaniv

In other Tierra-like systems the genotype is a sequence of instructions and the phenotype is the corresponding executed algorithm. This way the genotype-phenotype mapping is constrained by the structure of a creature’s processor, and this structure was fixed for an evolutionary scenario in previous systems. Our approach here is to put the mapping under evolutionary control. We use a universal p...

2000
Rajat Moona

This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a generic way. The processor models are written in a language called Sim-nML [1] which is powerful enough to capture the instruction set architecture of a processor. We describe a few tools in this paper which can be retarg...

1991
Matthew K. Farrens Andrew R. Pleszkun

The PIPE processor is an outgrowth of the PIPE Project, a research project at the University of Wisconsin-Madison whose goal was to investigate computer architectures that would be well suited to VLSI implementation. The implemented PIPE processor is a 32-bit pipelined single chip processor with a simplified load-store instruction set, a 5 stage pipeline, a two-cycle ALU, and the following uniq...

2011
Bolla Leela Naresh Purna Ramesh

This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been ext...

2012
R. Uma

RISC or Reduced Instruction Set Computer is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. So the main objective of this paper is to design and implement an 8-bit Reduced Instruction Set (RISC) processor us...

Journal: :IEEE Design & Test of Computers 2000
Margarida F. Jacome Gustavo de Veciana

This paper discusses research challenges in developing methodologies and tools for the synthesis and analysis of a key component in portable digital communications and multimedia consumer electronics systems, namely, application-specific processors and associated compilers. For such applications it is typically desirable to implement functionality in software, however the penalty in cost/effici...

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