This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for Bluetooth low-energy (BLE) transceiver in 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including gm cell locations and Al metal layer, were implemented, performance was compared verified BLE application. The implemented neck (NDCO), where is located main indu...

We present data layout transformation as an effective performance optimization for memory-bound structuredgrid applications for GPUs. Structured grid applications are a class of applications that compute grid cell values on a regular 2D, 3D or higher dimensional regular grid. Each output point is computed as a function of itself and its nearest neighbors. Stencil code is an instance of this app...

MOTIVATION Properly drawn biological networks are of great help in the comprehension of their characteristics. The quality of the layouts for retrieved biological networks is critical for pathway databases. However, since it is unrealistic to manually draw biological networks for every retrieval, automatic drawing algorithms are essential. Grid layout algorithms handle various biological proper...

Quality and value of an IC product are functions of power, performance, area, cost and reliability. The forthcoming 2013 ITRS roadmap observes that while manufacturers continue to enable potential Moore’s Law scaling of layout densities, the “realizable” scaling in competitive products has for some years been significantly less. In this paper, we consider aspects of the question, “To what exten...

Two commonly used keypad arrangements are the telephone and calculator layouts. The purpose of this study was to determine if entering different types of numeric information was quicker and more accurate with the telephone or the calculator layout on a computer keyboard numeric keypad. Fifty-seven participants saw a 10-digit numeric stimulus to type with a computer number keypad as quickly and ...

This paper describes the design and development of a module generator for a dual-rail PLA with embedded 2-input logic cells for 0.35 μm CMOS technology. In order to automatically generate logic-cell based PLA layouts from circuit specifications, a module generator as a design automation tool of logic-cell based PLA is developed with a structural improvement. This module generator is based on a ...

For robust standard cell design, designers need to improve the intercell compatibility for all combinations of cells and cell placements. Multiple patterning lithography colorability check breaks the locality of traditional rule check, and N-wise checks are strongly needed to verify the colorability for layout interactions across cell boundaries. A systematic framework is proposed to evaluate t...

This document provides a brief proposal for “Robust Optimization & Robust Control Synthesis” reading group.

In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. Yet, most of the layout design is still handmade, essentially because analog designers want to have total control over the different design options, and also, due to the fact that current fully automated genera...