T h e testabili ty of a sequential circuit can be i m proved by controlling the clocks of individual storage elements during testing. W e propose several clock control strategies derived f r o m a n analysis of the circuit, i t s S-graph structure, and i ts funct ion. Through examples we show how the number of clocks aflects the circuit’s testability. It i s shown that if certain flip-flops (FF...

ed state machines Deterministic state machines 1. State machine extraction (e.g. stg_extract) 2. Eliminate conditions New constraints in ITL 3. Sequential circuits 5. Logic synthesis 4. Sythesizer (tableau and determinize) KISS2 interface Figure 2: Flow of Our Redesign Method 4 A Redesign Method We cannot handle very complex ITL formulas within a reasonable time, since the expansion time grows ...

The goal of blif is to d escribe a logic-level hierarchical circuit in textual form. A circuit is an arbitrary combinational or sequential network of logic functions. A circuit can be viewed as a directed graph of combinational logic nodes and sequential logic elements. Each n o d e h as a two-level, single-output logic function associated with it. Each feedback l o o p m ust contain at least o...

In the past, the major issue of the VLSI designer were area, cost, performance, and reliability; power consideration was mostly of only inferior importance. But over the last few years power in the circuit is the major problem now days which is being faced by the very large scale integration industries. The power dissipation in any circuit is usually take place by the clocking system which incl...

This paper presents a switch-level test generation system for synchronous sequential circuits in which a new algorithm for switch-level test generation and an existing fault simulator are integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models all aspects of switch-level behavior. The time-frame based algorithm uses asynchronous processing wit...

Power estimation is an important issue in digital VLSI circuit design. The estimation of average power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this paper, two algorithms based on least square estimation are proposed for determining the average power dissipation in CMOS circuits. Least square estim...

Data parallel simulation involves simulating the behavior of a circuit over a number of test sequences simultaneously. Compared to other parallel simulation techniques, data parallel simulation requires less overhead for synchronization and communication, and it permits higher degrees of parallelism. We have implemented two data parallel versions of the switch-level simulator COSMOS. The rst ru...

The action system framework for modelling parallel programs is used to formally specify a microprocessor. First the microprocessor is speciied as a sequential program. The sequential specii-cation is then decomposed and reened into a concurrent program using correctness-preserving program transformations. Previously this microprocessor has been speciied in a semi-formal manner at Caltech, where...

The paper presents two functional fault models that are devoted for functional delay test generation for non-scan synchronous sequential circuits. The sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the length of clock sequence. The method that allows determining the length of clock sequen...

We suggest the use of a declarative programming language to design and describe circuits, concentrating on the use of higher-order functions to structure and simplify designs. In order to describe sequential circuits, we use a language , fp, which abstracts from temporal iteration. The practicalities of vlsi design make regularity attractive, and we describe the use of familiar higher order fun...