In this study, a simple chaos communication system including modulation-demodulation circuits is studied. The influence of modulation-demodulation circuits to chaos synchronization is investigated. For the estimation of communication quality, bit error rate (BER) is calculated by computer simulation when a sequential random pulse information signal is transmitted via this proposed system. key w...

We study the effect of the controller on the testability of sequential circuits composed of controllers and data paths. We show that even when all the loops of the circuit have been broken by using scan flip-flops (FF’s) and the control and data path parts are individually 100%testable, the composite circuit may not be easily testable by gatelevel sequential automatic test pattern generation (A...

We present a new approach to built-in self-test of sequential circuits using precomputed test sets. Our approach is especially suited to circuits containing a large number of ipops but few primary inputs. Such circuits are often encountered as embedded cores and lters for digital signal processing, and are inherently di cult to test. We show that statistical encoding of test sets can be combine...

Binary decision diagrams (BDDs) are used for automatic synthesis and formal verification of combinational and sequential circuits. However, a larger adoption of these technologies for sequential designs still depends on a more efficient use of BDDs. One important factor is the order of the variables in the BDD, which has a direct impact on the space (and time) requirements of the reachability a...

Bounds on test sequence length can be used as a testability measure. We give a procedure to compute the upper bound on test sequence length for an arbitrary sequential circuit. We prove that the bound is exact for a certain class of circuits. Three design rules are specified to yield circuits with lower test sequence bounds.

An algorithmic paradigm for I DDQ measurement based analysis that target all two node bridging faults (BFs) in CMOS circuits is presented. In contrast to the pessimistic criteria used in our prior work, here we use the criteria for identifying I DDQ tests proposed in the literature by other researchers. Algorithms for simulation, diagnosis and I DDQ subset selection of BFs in combinational circ...

Among the main algorithmic problems in the veriication of sequential circuits are the computation of good orders of state variables and transition relation partitions. Existing model checking packages like SMV from CMU, VIS from Berkeley or Rulebase from IBM Haifa provide variants of Rudell's sifting algorithm for the variable ordering problem and greedy-type algorithms for the partition orderi...

This short paper describes a well-known and a non-standard technique for proving properties about sequential circuits. The techniques are based on transforming the circuit to an abstract state machine, and performing several ways of induction on these state machines. We conclude with an insightful correspondence between the two techniques. The proposed methods have been implemented in an experi...

we propose the design of two vectors testable sequential circuits based on conservative logic gates. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, masterslave flip-flops and double edge triggered (DET) flip-f...

Narendra Shenoy Richard Rudell Synopsys Inc., 700 E. Middle eld Road, Mountain View CA 94043 Abstract Retiming is a technique for optimizing sequential circuits. It repositions the registers in a circuit leaving the combinational cells untouched. The objective of retiming is to nd a circuit with the minimum number of registers for a speci ed clock period. More than ten years have elapsed since ...