Mats Høvin1, Alf Olsen2, Tor Sverre Lande1 and Chris Toumazou3 1Dept. of Informatics, University of Oslo, Blindern, N-0316 Oslo, Norway 2Schlumberger Geco-Prackla, Jongsåsveien 4, N-1300 Sandvika, Norway 3Dept. of Electrical & Electronic Engineering, Imperial College, Exhibition Road, London SW7 2BT, UK Abstract— This paper describes a new first and secondorder delta-sigma modulator (DSM) conce...

This paper presents a mixed equation-based and simulation-based design methodology for continuous-time Sigma-Delta modulators from high level specifications down to Layout. The calculation and scaling of the SigmaDelta coefficients as well as circuit sizing and layout generation are implemented in the same analog design environment CAIRO+. The design of a complete third order current-mode conti...

A recent sigma-delta modulator architecture incorporates spectral shaping of hardware-mismatch errors through redundancy introduced by embedding the input/output subspace in a higher-dimensional space for loop operation. Here basic design issues for the key vector quantizer and matriximpulse-response loop filter are explored. A simple design example and simulation illustrate.

A reduced complexity digital multi-stage noise shaping (MASH) delta–sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to “1;” shorter words are used in subsequent stages. Experimental results confirm simulations.

A MASH digital delta–sigma modulator (DDSM) is analyzed mathematically. It incorporates first-order error feedback modulators (EFM) which include prime modulus quantizers to guarantee a minimum sequence length . The purpose of this analysis is to calculate the exact sequence length of the aforementioned MASH DDSM. We show that the sequence length for an th-order member of this modulator family ...

In this paper, a complete high-speed Continuous-Time Bandpass Delta-Sigma modulator for digital receiver applications is modeled, using VHDL-AMS. The main Continuous-Time DeltaSigma modulator’s nonidealities such as excess loop delay, clock jitter and multi-bit feedback DAC element mismatch in the modulator loop are also modeled and their effects evaluated. An accurate understanding of these no...

This paper presents a third-order Sigma-Delta modulator that uses only two operational amplifiers. A fully digital solution reduces both amplifiers output swings. This design achieves complex conjugate zeros that allows obtaining a signal-to-noise ratio of about 8 dB better than having all the zeros placed at z = 1. Behavioral level simulations demonstrate the effectiveness of the approach.

This paper addresses the problem of pattern noise encountered in single-stage delta-sigma modulators in the presence of a DC input signal. By utilizing state-space matrices, we explain the cause of these undesired cyclic patterns and show how a modulator’s susceptibility to tonal behavior can be determined by inspection of the system matrix A. By example of two frequently used single-stage arch...

This paper describes the implementation of a low-voltage, wide bandwidth, continuous-time low-pass ∆Σ modulator. The presented modulator operates at a supply voltage of 1.8V and can achieve a maximum SNDR of 74dB (more than 12 bits) for an oversampling ratio of 32 and in a bandwidth of 2.5 MHz

In this paper, a novel class of Sigma-Delta modulators is presented. The usual scalar 1-bit quantizer in a Sigma-Delta modulator is replaced by a 1-bit vector quantizer with a Ndimensional input statevector from the linear feed-back fdter. Generally, the vector quantizer changes the nonlinear dynamics of the modulator, and a proper choice of vector quantizer can improve both system stabilitg an...