Silicon-on-insulator (SOI) devices have many advantages, such as high speed, low energy consumption, radiation-hard, and integration. In this paper, the separation by implanted oxygen process under low-dose implantation conditions is studied two-step method combined with internal thermal oxidation process. The effects of different types silicon wafers doses on SOI surface defects, top Si thickn...

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits disp...

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parame...

This paper presents the development and characterization of a new high-aspect-ratio MEMS process. The silicon-on-silicon (SOS) process utilizes dielectric barrier discharge surface activated low-temperature wafer bonding and deep reactive ion etching to achieve a high aspect ratio (feature width reduction-to-depth ratio of 1:31), while allowing for the fabrication of devices with a very high an...

Silicon on insulator (SOI) technology permits a good solution to the miniaturization as MOSFET size scales down. This paper is about compare electrical performance of nanoscale FD-SOI at various gate lengths. The compared and contrasted with help threshold voltage, subthreshold slope, on-state current leakage current. Interestingly, by decreasing length, are increased but voltage decreased sub-...

The use of compliant silicon-on-insulator ~SOI! substrates instead of Si substrates is shown to improve the quality of epitaxial GaN layers by releasing the strain and absorbing the generated threading dislocations in the thin Si overlay of the SOI substrate. GaN layers have been grown on SOI substrates by low-pressure metalorganic chemical vapor deposition and various growth conditions and com...

Silicon photonics enables large-scale photonic-electronic integration by leveraging highly developed fabrication processes from the microelectronics industry. However, while a rich portfolio of devices has already been demonstrated on the silicon platform, on-chip light sources still remain a key challenge since the indirect bandgap of the material inhibits efficient photon emission and thus im...

The engineering of strained semiconductor materials represents an important aspect of the enhancement in CMOS device performance required for current and future generations of microelectronic technology. An understanding of the mechanical response of the Si channel regions and their environment is key to the prediction and design of device operation. Because of the complexity of the composite g...

Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used improve linearity operational amplifiers. Two amplifiers designed and fabricated a 22 nm technology illustrate this technique, as well its advantages limitations.