The importance of semiconductor wafer fabrication has been increasing steadily over the past decade. Wafer fabrication is the most technologically complex and capital intensive phase in semiconductor manufacturing. It involves the processing of wafers of silicon in order to build up layers and patterns of metal and wafer material. Many operations have to be performed in a clean room environment...

The dehydrogenation of intrinsic hydrogenated amorphous silicon (a-Si:H) at temperatures above approximately 300 °C degrades its ability to passivate silicon wafer surfaces. This limits the temperature of post-passivation processing steps during the fabrication of advanced silicon heterojunction or silicon-based tandem solar cells. We demonstrate that a hydrogen plasma can rehydrogenate intrins...

In this letter, we report a novel approach to selectively functionalize the surface of silicon nanowires located on silicon-based substrates. This method is based upon highly localized nanoscale Joule heating along silicon nanowires under an applied electrical bias. Numerical simulation shows that a high-temperature (>800 K) with a large thermal gradient can be achieved by applying an appropria...

A new type of HF solution, HF-acetonitrile (MeCN), has been employed to produce 10–30 Am thick porous silicon (P-Si) layers by photoelectrochemical etching of different types of Si wafers, Si(100), Si(111) and polycrystalline Si, with different resistivities. A combined optical, surface and nuclear microscopic assessment of these P-Si layers was performed using photoluminescence (PL), Raman sca...

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace ...

A wafer level surface activated bonding ~SAB! tool has been developed for microelectromechanical systems ~MEMS! packaging at low temperature. The tool accommodates 8 in. diam wafers. The principle features of the tool are the automatic parallel adjustment for 8 in. wafers to a margin of error within 61 mm and the X, Y, and u axis alignments with an accuracy of 60.5 mm. We have approached a new ...

Two sets of silicon wafers were implanted with 60 keV arsenic ions at a dose of 5x1015 cm-2, using an Applied Materials SWIFT implanter. The first batch consisted of five silicon preamorphised wafers, whilst the second batch was implanted under the same conditions into <100> single crystal wafers. The tilt angle was varied over the range 0o 45o. After implantation the samples were cut into smal...