This paper addresses a built-in self-test (BiST) for ICs digital transceivers. The focus is on testing the RF frontend while taking advantage of the on-chip DSP resources and DA-, AD converters. The loopback architecture is used to prevent the sensitive RF blocks from extra noise and external disturbances. The test aims at spot defects typical of RF CMOS ICs, where those faults are deemed the m...

This paper presents a pulse response-based builtin self test technique and implementation for the testing of analog integrated circuits in mixed-signal systems. This BIST technique employs two narrow width pulses as input stimuli, and monitors two voltage samples on pulse response waveform for fault detection through allowable tolerances. The BIST system implementation realizes a programmable d...

This report introduces new design and synthesis techniques that reduce the area and improve the performance of embedded built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths so that some of the BIST and scan logic is shared with the system logic. Logic sharing is possible when scan dependence is introduced in...

Memory-Built In Self-Test (MBIST) is an very effectual and output enrichment for embedded RAMs. This paper presents effectual MBIST concepts of Built-In-Self Test (BIST) using Performance Accelerator Algorithm (PAA). This BIST concept very stretchable for embedded RAMs with suitable operation. PA algorithm efficiently detects probable number of fault models compare to other March test algorithm...

The structure of test system based on application built-in self-test (BIST) circuitries has been proposed. The main idea is oriented on minimization of hardware overheads and dealt with automatization of BIST-circuitries generation. Test generator based on linear feedback shift register (LFSR) provides two types of testing pseudorandom and deterministic. The proposed modified Berlekamp–Massey a...

A BIST (Built-In Self-Test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (Circuit Under Test) by configuring the circular path as a partial scan chain. A CAD (Computer-Aided Design) tool for automating this...

Built-in Self-Test (BIST) approaches for Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGAs) must be capable of fully testing the resources in the device. A summary of current techniques is presented in this paper that covers the three main components of modern FPGAs: logic blocks, interconnects and embedded FPGA cores. Overhead requirements, coverage capability, tra...

A recon gurable data converter (RDC) that can be con gured to a number of ADCs and DACs having different speeds and resolutions for testing mixed-signal systems is proposed. It can be used as a building block in mixed-signal boundary scan or built-in self test (BIST) techniques. The RDC can also be con gured as random noise generators and used as test stimuli in BIST. Since the required area of...

The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose...

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for hig...