In this article threshold gates with hysteresis using neuron MOS (νMOS) are presented as basic elements in Null Convention Logic (NCL) circuits. NCL, which proposed by K. M. Fant and S. A. Branst, needs special gates having hysteresis, because NCL uses different ternary logic systems in computation phase and wiping phase of asynchronous behavior, respectively. To impliment the dinamic behavior,...

This paper presents a compact multiple-valued maskprogrammable logic array (MPLA) based on a MINITSUM (MINimunl/Truncated-SU~~ two-level synthesis, A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MINplane. Since a threshold literal can be designed by using a singlejoating-gate MOS transistor,...

All-optical 2R logic regeneration is demonstrated using a vertical cavity semiconductor optical amplifier. The optical switching threshold is 1 μW, with 10 dB gain and >6:1 (8dB) extinction ratio. Performance limits are also discussed. ©2003 Optical Society of America OCIS codes: (190.1450) Bistability; (200.4660) Optical Logic; (250.5980) Semiconductor Optical Amplifiers; (230.4320) Nonlinear ...

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design on the leakage reduction mechanism. A multi-threshold logic is employed for reducing current during read/write operations. Here, technique used to insert high threshold sleep control low circuit. The insertion performed in serial manner. transistors are very useful deriving su...

The main result is the development of a low depth, highly compact implementation of parallel counters (i.e., population counters), based on threshold logic. ?\U0 such counters are designed using the recently proposed Charge Recycling Threshold Logic (CRTL) gate. The novel feature of the designs is the sharing among 311 threshold gates of a single capacitive network for computing the weighted su...

This paper presents a ternary half adder and 1-trit multiplier using carbon nanotube transistors. The proposed circuits are designed pass transistor logic dynamic logic. Ternary uses less connections than binary logic, voltage changes required for the same amount of data transmission. Carbon transistors have advantages over MOSFETs, such as mobility electrons holes, ability to adjust threshold ...

Carbon nanotube field-effect transistors (CNFETs) are a promising candidate to replace conventional metal oxide field-effect transistors (MOSFETs) in the time to come. They have considerable characteristics such as low power consumption and high switching speed. Full adder cell is the main part of the most digital systems as it is building block of subtracter, multiplier, compressor, and other ...