Low noise amplifier is the front end block of radio-frequency receiver system. Its design required various characteristics such as power gain, noise figure, insertion losses and power consumption. In this paper we have proposed a single stage low noise amplifier design with high gain and low noise using inductive source degeneration topology for frequency range of 3 GHz to 7 GHz and also use th...

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A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology. With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.

An ultra low power consuming low noise amplifier (LNA) at C-band with variable gain for adaptive antenna combining is presented in this paper. The microwave monolithic integrated circuit (MMIC) was fabricated using commercial 0.25 μm bipolar complementary metal oxide semiconductor (BiCMOS) technology. At 5.2 GHz, a supply voltage of 1.2 V and a current consumption of only 1 mA, a maximum gain o...

A novel ultra high speed, compact and least sensitive to process variation, hybrid sense amplifier is designed for ultra low power SRAM. Precisely sized current mode circuit (CMC) is designed to provide differential current from bit-lines. We eliminate the global sensing stage to save silicon area and sized the output buffers to achieve full logic swing at the output of proposed sense amplifier...

Problem statement: The Low Noise Amplifier (LNA) is a core block of an Ultra Wide Band (UWB) receiver since it amplifies a very weak signal received at the antenna to acceptable levels while introducing less self-generated noise and distortions. The LNA design poses a unique challenge as it requires simultaneous optimization of various performance parameters like power gain, input matching, noi...