BACKGROUND The aim of this study was to compare the biomechanical characteristics between bilateral and unilateral lumbo-iliac fixation in unilateral comminuted sacral fractures (USF) by finite element analysis. METHODS A 3-dimensional finite element model of unilateral sacral fractures was simulated. Three kinds of implants were instrumented into the model, including the unilateral lumbopelv...

While there is a lot of research about other aspects of game design, there are fairly few studies about music and sound in video games. Since music and sound are components of next to all games, it is interesting to investigate how this aspect affects the perceived immersion of gamers. The aim of this study is to investigate how sound and music affect player sense of presence in a video game, T...

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of previous methods. We describe which figures of merit, including the logical effort, affect the design quality of a cell transistor network. Further, ...

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is not switching. Estimates suggest a five-fold increase in leakage energy in every future generatio...

In this paper, we have proposed the concept of 7Transistor SRAM. 7-Transistor SRAM has been designed to provide an interface with CPU and to replace DRAM in systems that require very low power consumption. The feature of 7Transistor SRAM like low power consumption and leakage current have been analyzed with 45nm technology. The comparative study and mathematical modeling have been proposed for ...

A unified approach to RF and microwave noise parameter modeling in bipolar transistors is presented. Circuit level noise parameters including the minimum noise figure, the optimum generator admittance, and the noise resistance are analytically linked to the fundamental noise sources and the y-parameters of the transistor through circuit analysis of the chain noisy two-port representation. Compa...

In this paper, a simple behavior-level fault model, which is able to represent the faulty behavior of the closed-loop operational amplifier (OP), is presented. The fault model, derived from the macro equivalent circuit of the OP but verified with transistor level simulation, consists of the offset fault and the limited-current fault. It can represent the faulty behavior of the closed loop OP of...

Although there is still controversy about its origin, the designer requires accurate models to estimate 1/f noise of the MOS transistor in terms of its size, bias point and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel association of transistors and they may not provide adequate results for all the operation regions, particul...

As new technologies use a reduced transistor size to improve performance, circuits are becoming remarkably sensitive to soft errors that become a serious threat for critical applications reliability. Most of the existing reliability enhancing techniques lead to costly hardware. The masking phenomenon is fundamental to accurately estimating soft error rates (SER). The first contribution of this ...

We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. This new model combines the advantages of both RT-level and gate-level approaches. We investigate the relationship between steadystate transition power and overall power dissipation. We observe that, statistically, two input sequences causing similar amount of steady-state transitions will exhibit ...