We present a framework that verifies and maintains the consistency between the representations of the form, function and behavior of mechatronic devices. These three aspects of the device represent the geometry, the task, and the actions taken to realize the task, respectively (Pahl and Beitz, 1996). They evolve simultaneously through the design process. When the designer makes a change to one ...

In this paper, the design and implementation of a real-time traffic light control system based on Fieldprogrammable Gate Array (FPGA) technology is reported. The traffic light control system is designed with VHDL language. Its function was verified with simulation. After that, the VHDL design was downloaded to FPGA board hardware to verify its function in experiment. The designed traffic light ...

This paper addresses the problem of formally verifying VHDL descriptions. More precisely, we check the correctness of a VHDL architecture w.r.t. another architecture of the same entity. Both of them are translated into recursive functional forms, and the proof of their equivalence is realized by means of the Boyer-Moore theorem prover. Our methodology is illustrated by a signi cant example that...

VHDL models for neural networks for automatic test generation of gate level circuits are presented in this paper. A program converts a gate netlist to its equivalent neural model. A good circuit and faultable bad circuits will be generated. A VHDL test bench has been developed to apply the faults to the neural network bad circuit model, and report tests that are generated for each injected fault.