The size and complexity of present day VLSI integrated circuits (IC) and systems demands the elimination of repetitive manual operations and computations in their design. This motivates the development of automatic design systems. Automation of a given (design) process requires its algorithmic analysis. The availability of fast and easily implementable algorithms is essential for the discipline...

Power consumption plays an essential role in VLSI design. Earlier, the VLSI designers were more concentrated on performance and area, but, gradually, low power consumption became one of the most important factors in VLSI design. Increasing demand and growth of portable devices have increased the demand of power efficient VLSI circuits. In this paper, various conventional low power designs are a...

The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay...

This research presents for thejrst time an integer optimization approach for scheduling video computations on bus-constrained VLSI architectures or on an existing VLIWprocessor. For many video systems a combination of processor and VLSI chip provides a low cost solution that meets given performance requirements. Thus tools for analyzing whether a video function is best implemented in hardware (...

This paper examines the impact of VLSI technology on the evolution of computer architecture and projects the future of this evolution. We see that over the past 20 years, the increased density of VLSI chips was applied to close the gap between microprocessors and high-end CPUs. Today this gap is fully closed and adding devices to uniprocessors is well beyond the point of diminishing returns. To...

In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF × NF ) with O((NF )3) complexity to some FFT operations with O(NF log2(F )) complexity and the inverse of some (N × N) sub-matrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization a...