We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m × n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of...

Processed meat intake is associated with increased risk of colorectal cancer. This association may be explained by the endogenous formation of N-nitroso compounds (NOC). The hypothesis that meat intake can increase fecal NOC levels and colon carcinogenesis was tested in 175 Fischer 344 rats. Initiation was assessed by the number of aberrant crypt foci (ACF) in the colon of rats 45 days after th...

Due to the interplay between increasing chip capacity and complex applications, System-on-Chip (SoC) development is confronted by severe challenges, such as managing deep submicron effects, scaling communication architectures and bridging the productivity gap. Network-on-Chip (NoC) has been a rapidly developed concept in recent years to tackle the crisis with focus on network-based communicatio...

Network on Chip (NoC) is a communication framework for the Multiprocessor System (MPSoC). It router-based system. In NoC architecture, nodes of MPSoC are communicating through network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent DyAD, and DyXY. The main problems in these congestion faults. Congestion faults cause delay, which degrades performance NoC....

In this paper we present our design and implementation of Network-on-Chip (NoC) support into our TACO protocol processor architecture. Our signaling scheme is Virtual Component Interface standard (VCI) compliant. Due to the dataand I/O-intensive nature of protocol processing, memory access from I/O logic plays a key role in NoC interface design. We have addressed this problem by using dual-port...

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus it is important to carefully partition processing elements (PEs) into islands based on their workloads and communications. In this paper, we propose an energy-...

Multi-Processor System on Chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Net-works on Chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity grows, the problem emerges as how to design and instantiate such a NoC-based MPSoC platform in a syst...

Efficient NoC is crucial for communication among processing elements in a highly parallel processing systems on chip. Mapping cores to slots in a NoC platform and designing efficient routing algorithms are two key problems in NoC design. Source routing offers major advantages over distributed routing especially for regular topology NoC platforms. But it suffers from a serious drawback of overhe...

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication p...

The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless No...