Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop ...

As Technology progress deeper into submicron CMOS, traditional analog circuits face problems that are not to be solved purely by analog innovations. Instead, new architectures are being proposed which take advantages of the relatively cheaper of the digital circuits to augment or improve the diminishing performance of the analog circuitry. The conventional approach performs the design of 14 ban...

Regarding to the complexity and diversity of analog circuit fault, a principal component analysis(PCA) and particle swarm optimization(PSO) support vector machine(SVM) analog circuit fault diagnosis method is proposed. It uses principal component analysis and data normalization as preprocessing, then reduced dimension fault feature is putted into support vector machine to diagnosis, and particl...

Integrated circuit fabrication facilities are now offering digital system designers the ability to integrate analog circuitry and micromachined devices, but such mixed-technology microsystems are extremely difficult to design because of the limited verification and optimization tools available. In particular, there are no generally effective techniques for automatically generating reduced-order...

It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network SCCNN for analog signal processing circuits, designed the neural cell circuit, and developed the evolutionary design method of the SCCNN based on selfadapting genetic algorithm. In the architecture of new cellular neura...

An analog implementation of a deep machinelearning system for ef cient feature extraction is presented in this work. It features online unsupervised trainability and non-volatile oating-gate analog storage. It utilizes a massively parallel recon gurable current-mode analog architecture to realize ef cient computation, and leverages algorithm-level feedback to provide robustness to circuit imper...

Increasing numbers of analog components in today’s systems necessitate system level test composition methods that utilize onchip capabilities rather than solely relying on costly DFT approaches. We outline a tolerance analysis methodology for test signal propagation to be utilized in hierarchical test generation for analog circuits. A detailed justification of this proposed novel tolerance anal...

This paper is to review important device parameters as the figures of merit (FOM) to understand the device characteristics for analog/RF applications. These FOM should be characterized and evaluated in technology development and model generation for analog/RF technologies. This paper has tried to show these FOM with both measured data and model simulation to help both technology developers and ...

Modeling and simulation have been established as fundamental facilities in the development of analog and analog-digital systems. Essential advances have been achieved by the usage of behavioral modeling languages. These languages can be considered as a link between the technical problem and the mathematical model that can be evaluated by computational methods. The paper outlines the various pos...

This paper proposes a nonlinear oscillator network model for gray-level image segmentation suitable for massively parallel VLSI implementation. The model performs image segmentation in parallel using nonlinear analog dynamics. Because of the limited calculation precision in VLSI implementation, it is important to estimate the calculation precision required for proper operation. By numerical sim...