This paper reports the development of a low-power switchedcurrent algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter uses modified SI type current copiers to reduce the overall area and power consumption. The analog portion of the converter occupies only 0.35mm area in 3μm CMOS technology. The simulation results show that the converte...

There is an increasing demand for low power, low voltage, and small size analog readout bio-potential systems. This paper presents an analog front-end for measuring the intra-cardiac signals in implantable and also external ambulatory ECG cardiac recording applications. The analog front-end benefits from voltage to frequency conversion without conventional analog to digital conversion and there...

The continued drive toward technology scaling in VLSI design has provided greater integration levels in silicon chips. Thanks to the reduction in minimum feature size and the corresponding decrease in power supply voltage, digital circuits have benefited from savings in area and power consumption. This approach presents a number of challenges in Complementary Metal-Oxide Semiconductor (CMOS) an...

Digital logic integrated circuits are advancing toward ever higher speeds of operation. Clock frequencies already exceed 1 GHz in some Si CMOS-based consumer products, and even higher speeds are attainable in specialized technologies, such as those based on GaAs, InP, and SiGe bipolar and field-effect transistors. Digital approaches may be used to carry out a variety of functions important in m...

A key challenge in designing analog-to-digital converters for cortically implanted prosthesis is to sense and process high-dimensional neural signals recorded by the micro-electrode arrays. In this paper, we describe a novel architecture for analog-to-digital (A/D) conversion that combines Σ∆ conversion with spatial de-correlation within a single module. The architecture called multiple-input m...