To effectively strike a balance between system cost and accuracy, higher conversion accuracy is achieved by oversampling the low-resolution ADC integrated within a digital signal controller (DSC), and then processing the oversampled digital signal in software through a digital filter and a decimator. This processing scheme, which adds additional bits of accuracy to the 12-bit ADC conversion in ...

We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digitalto-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18μm CMOS process and consumes 118 μW at 1.8 V power supply...

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This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. T...

For 5G it will be important to leverage the available millimeter wave spectrum. Communication at high carrier frequencies requires antenna arrays at both the base and mobile station. A 1-bit analog to digital converter can effectively reduce the complexity and power consumption of the analog receiver frontend. This is especially interesting in the context of large antenna arrays with a sizable ...

To deal with the wide dynamic rage necessary for a radio receiver or corresponding applications, but to avoid impractically high resolution at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate reso...

An all-digital PWM-based delta-sigma (ΔΣ) ADC is proposed. This system takes advantages of the duration of a pulse, rather than voltage or current, as the analog operand used in its closed-loop operation. Unlike VCO-based ADCs, this ADC as a linear input sampling stage with adequate uncalibrated performance. Furthermore, the architecture allows inherently matched multi-bit quantizer/DAC blocks ...

In this paper, a reduced-sample-rate 2-2-0 deltasigma-pipeline analog-to-digital converter (ADC) is presented. The proposed architecture offers the possibility of implementing the reduced-sample-rate structure on higher order modulator without having stability or digital-to-analog converter (DAC) linearity problems. By the presented implementation approach some digital filters are eliminated, s...

The resolution and conversion speed of an Analog to Digital converter (ADCs) strongly depends on how efficiently Sampling Hold (S&H) circuit handles the amplitude skewing input analog signal. In this article, a novel S&H has been proposed handle errors produced because skewing. This two different paths for sampling holds process avoids non-ideal effects seen in most recent literature. p...

The demand for high resolution CMOS image sensors (CIS) is rising. Analog-to-digital converters (ADC) represent one of the major bottleneck of CIS. One of the candidates to overcome the existing limits is the column-parallel ADC. Column-parallel extended counting ADCs (EC-ADC) are able to reach high resolution thanks to their two-step conversion. However the EC-ADC area increases due to the two...