A set of CAD tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based upon the cost-table method. The general circuit structure, the cost-table functions and the decomposition procedure used in the cost-table synthesis program are explained. The synthesis program is based upon a logically complete set of...

Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on mem...

This paper presents a case study targeting the Aptix MP4 board and Xilinx VirtexE FPGAs, for digital TV application prototyping. The difficult FPGA prototyping issues typically encountered by engineers are illustrated on a big industrial example. Due to the increasing ASIC complexity, the basic challenge was to meet the project deadlines. To enable faster FPGA-based prototyping, both the ASIC d...

This paper shows how one single-chip ATM switch developed with ASIC technology has been modified to implement a reconfigurable ATM switch in a VIRTEX FPGA. With this new approach it is possible to develop a flexible ATM switch, using partial RTR to deploy new features to the network.

Within-die variations in path delays are increasing with scaling. Although higher levels of within-die delay variations are undesirable from a design perspective, they represent a rich source of entropy for applications that make use of ‘secrets’, such as authentication, hardware metering and encryption. Physical unclonable functions or PUFs are a class of circuit primitives that leverage withi...

Feel lonely? What about reading books? Book is one of the greatest friends to accompany while in your lonely time. When you have no friends and activities somewhere and sometimes, reading book can be a great choice. This is not only for spending the time, it will increase the knowledge. Of course the b=benefits to take will relate to what kind of book that you are reading. And now, we will conc...

Most chip producers perform delay testing to detect chips that are affected by defects that adversely affect timing. Several delay fault models have been introduced to guide delay test generation. But similar to static (i.e., slow speed) testing, there is always the question of which fault models are best for ensuring quality. MEasuring Test Effectiveness Regionally (METER) is an approach for e...

In this paper, hardware implementation aspects of the channel estimator in 3GPP LTE terminals are investigated. A channel estimation ASIC, which handles the real-time channel estimation, is presented. Compared to traditional correlatorbased channel estimators, the channel estimator presented boosts the throughput at feasible silicon cost by adopting a recently proposed estimation method named A...

This paper describes a fast, low-complexity, entropy efficient video coder for wavelet pyramids. This coder approaches the entropy-limited coding rate of video wavelet pyramids, is fast in both hardware and software implementations, and has low complexity (no multiplies) for use in ASICs. It consists of a modified Z-coder used to code the zero/non-zero significance function and Huffman coding f...