A semi-custom high-speed datapath design flow is described using commercial ASIC design CAD tools interacting with a simple hierarchical placement Matlab code. The flow leverages the vast automation and verification capabilities of ASIC design CAD tools, while providing a precision close to a fully custom-designed circuit. The methodology is applied to the design of a 4channel, 3-GHz per-channe...

This paper presents an ultra low noise instrumentation based on a standard BiCMOS SiGe 0.35 μm ASIC operating at cryogenic temperatures. The main functions of the electronic circuit are the readout and the multiplexing of SQUIDs/TES. We report the cryogenic operation of the ASIC dedicated to the readout of a 2x4 pixel demonstrator array. We particularly emphasize on the development and the test...

We introduce an approach for design and optimization of ASIC implementations which realize multiple computational tasks under hard real-time constraints. The approach designs a multitask ASIC by combining techniques from hard real-time scheduling and behavioral synthesis. The key component of the methodology is successive multiresolution synthesis technique. The technique starts from an incompl...

This paper presents a case study targeting the Aptix MP4 board and Xilinx VirtexE FPGAs, for digital TV application prototyping. The difficult FPGA prototyping issues typically encountered by engineers are illustrated on a big industrial example. Due to the increasing ASIC complexity, the basic challenge was to meet the project deadlines. To enable faster FPGA-based prototyping, both the ASIC d...

Amil: amiloride ASIC: acid-sensing ion channel GMQ: 2-guanidine-4-methylquinazoline EGTA: ethylene

In this paper an OFDM timing synchronization ASIC is presented. The proposed synchronization unit can be used in any OFDM system. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where the time offset is estimated. Although the algorithm is too complex to be implemented on today’s most powerful standard DSP, a hardware architecture...

Abstract We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for CMS Endcap Timing Layer (ETL) High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in 65 nm CMOS technology, reads out 16× 16 pixel matrix Low-Gain Avalanche Detector (LGAD). jitter contribution from is required to be below 40 ps achieve 50 overall time reso...

A boundary-scan logic design method that depends only on level-sensitive scan design (LSSD) principles has been developed for IBM CMOS application-specific integrated circuit (ASIC) products. This technique permits comprehensive testing of LSSD ASlCs with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic test equipment (ATE). This paper describe...

Fast Prototyping of Memory Models in VHDL for Hardware Emulation p. 108 New Design and Prototyping Methods are Needed in Missile Electronics Industry p. 116 Industrial Approach in Design Methodologies for Mobile Communication Systems p. 122 ASIC Prototyping with Reprogrammable Implementations of Large ASICs p. 127 Rapid-Prototyping of Embedded Systems via Reprogrammable Devices p. 133 CO: The C...