Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime the circuit delay, and hence, the leakage energy consumption depend on the supply voltage exponentially. By reducing the idle time of the circuit, the energy-minimum supply voltage can be reduced, resulting in lower energy consumption. This paper firs...

Formal verification is increasingly important in asynchronous circuit design, since the lack of a global synchronizing clock makes errors due to concurrency (e.g., deadlocks) virtually impossible to detect by means of conventional methods such as simulation. This paper presents a hierarchical approach to asynchronous systems verification using CSP and its model checker FDR. The approach reflect...

For high performance designs, dynamic logic styles are in the focus due to the promising high reachable frequencies. True Single Phase Clock (TSPC) logic yields easy to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree design and high power consumption. Asynchronous logic has the potential to solve these problems. Asynchronous Chain (AC)-...

We characterize the user capacity, i.e., the maximum number of supportable users at a common SIR target level for a fixed processing gain, of a single-cell symbol asynchronous CDMA system. We show that the user capacity of an asynchronous system is the same as the user capacity of a synchronous system; that is there is no loss in user capacity due to asynchrony. Optimum signature sequences are ...

This paper presents a new framework for asynchrony. This has its origins in our attempts to better harness the internal decision-making process of cellular automata (CA). Thus, we show that a max-plus algebraic model of asynchrony arises naturally from the CA requirement that a cell receive the state of each neighbor before updating. The significant result is the existence of a bijective mappin...

A testing scenario in the sense of De Nicola and Hennessy is developed to measure the worst-case eeciency of asynchronous systems using dense time, and it is shown that one can equivalently use discrete time. The resulting testing-preorder is characterized with some kind of refusal traces. Furthermore, the testing-preorder is reened to a precongruence for standard operators known from process a...

In this paper we present FASE (Fast Asynchronous Systems Evaluation), a tool for evaluating worst-case efficiency of asynchronous systems. This tool implements some well-established results in the setting of a timed CCS-like process algebra: PAFAS (a Process Algebra for Faster Asynchronous Systems). Moreover, we discuss some new solutions that are useful to improve the applicability of FASE to ...

T HE SPECIAL Section in this issue covers different aspects of asynchronous design. This is an area of increasing interest in the last few years triggered by the new challenges dictated by the continuous miniaturization of integrated circuits. Variability, power, noise, and electromagnetic interference are some of the aspects that designers have to face today to make their circuits efficient, r...

Complexin (Cplx) proteins modulate the core SNARE complex to regulate exocytosis. To understand the contributions of Cplx to signaling in a well-characterized neural circuit, we investigated how Cplx3, a retina-specific paralog, shapes transmission at rod bipolar (RB)→AII amacrine cell synapses in the mouse retina. Knockout of Cplx3 strongly attenuated fast, phasic Ca(2+)-dependent transmission...