This paper addresses the problem of building a Boolean dataflow network (sequential circuit) recognizing the language described by a regular expression. The main result is that both the construction time and the size of the resulting network are linear with respect to the size of the regular expression.

We introduce a substructural propositional calculus of Sequential Dynamic Logic (SDL) that subsumes a propositional part of dynamic predicate logic (DPL), and is shown to be expressively equivalent to propositional dynamic logic (PDL). Completeness of the calculus with respect to the intended relational semantics is established.

A control methodology for asynchronous sequential machines is addressed in this paper. The considered machine consists of a number of input/state asynchronous machines, termed submachines, between which asynchronous switching is conducted by the switching signal. The control objective is to design a corrective controller so that the stable-state behavior of the closed-loop system can mimic a re...

Most of the microelectronic circuits fabricated today are synchronous, i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high-speed clock distribution, integration of multiple cores operating at different clock rates, reduction of power consumption and dealing with voltage, temperature, manufacturing and runtime variati...

A strategy of fault diagnosis and tolerance for asynchronous sequential machines is discussed in this paper. With no synchronizing clock, it is difficult to diagnose an occurrence of permanent or stuck-in faults in the operation of asynchronous machines. In this paper, we present a fault detector comprised of a timer and a set of static functions to determine the occurrence of faults. In order ...

In this paper, we propose a technique for hardware implementation of protocol specifications in LOTOS. For the purpose, we define a new model called synchronous EFSMs consisting of concurrent EFSMs and a finite set of multi-rendezvous indications among their subsets, and propose a conversion algorithm from a subset of LOTOS. The derived synchronous EFSMs can be easily implemented as a synchrono...

Over the years, there have been numerous methods proposed to solve the synchronization problem. Many of these methods, however, are not sufficiently evaluated before being utilized leading to problems in a system design that are difficult to diagnose and solve. Therefore, it is crucial that strategies for synchronization are critically analyzed and verified before being incorporated in a system...

Recently, there has been a resurgence of interest in asynchronous design techniques due to the potential of asynchronous logic for higher performance, power ef-ciency and immunity from clock-related timing problems. Occam, a CSP-based parallel language provides for the rapid development of asynchronous architectural simulation models which may then be executed on a transputer network to achieve...

This paper examines the dynamic fault behavior of asynchronous sequential machines, specifically identifying the faults which cause critical races and hazards, and presents a state assignment technique leading to a machine that enters one of a small set of error states whenever a fault occurs. Entry into an error state can be checked by very simple check circuits; a self-testing check circuit a...