Published work on stuck-at fault test generation nearly exclusively considers circuits composed of only binary logic gates. Industrial designs commonly contain three-state elements , such as: busses and drivers, transmission gates, and bidirectional I/O. This paper presents extensions to state-of-the-art ATPG algorithms in order to handle these elements. A 25-valued signal model is used for tes...

Due to the continuous increase in the size and complexity of VLSI circuits, Automated Test Pattern Generation (ATPG) [ABFr90] is now a major problem from the industrial and economic point of view. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational and small sequential networks. Very large sequential circuits, however, still constitu...

This paper proposes novel algorithms for computing test patterns for transition faults in combinational circuits and fully scanned sequential circuits. The algorithms are based on the principle that s@ vectors can be effectively used to construct good quality transition test sets. Several algorithms are discussed. Experimental results obtained using the new algorithms show that there is a 20% r...

The issue of SOC testing is one of the most crucial in their design and production process. A popular solution for SOCs including microprocessor cores is based on letting them execute a test program, thus implementing a very attracting BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor starting from its RT-level description. Th...

This paper proposes a new approach for designing a cost-effective, on-chip, hardware pattern generator of deterministic test sequences. Given a pre-computed test pattern (obtained by an ATPG tool) with predetermined fault coverage, a hardware Test Pattern Generator (TPG) based on Autonomous Finite State Machines (AFSM) structure is synthesized to generate it. This new approach exploits “don’t c...

This paper presents an industrial case study on Built-In Self-Test for random logic (LBIST). The Self-testing Using MISR and Parallel SRSG (STUMPS) approach combined with multi-phase test point insertion (MTPI) has been evaluated on twenty-two industrial proven cores. The whole LBIST flow, including making cores LBIST ready and insertion of test points, has been investigated. The consequences w...

We introduce a new type of test, called exclusive test, and discuss its application to fault diagnosis in combinational circuits. A test that detects exactly one fault from a given pair of faults is called an exclusive test. In general, generation of an exclusive test by a conventional automatic test generator requires a model of the circuit with multiple-faults. We describe an ATPG model that ...

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm test length and fault coverage as well are optimized. However, there are circuits with bad random testability properties, that are also hard to test using genetically optimized test patterns. Thus, dete...

This paper describes an environment for internetbased collaboration in the field of design and test of digital systems. Automatic Test Pattern Generation (ATPG) and fault simulation tools at behavioral, logical and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented. The interfaces between the integrated t...

The feasibility of generating high quality functional test vectors f o r sequential circuits using the Growth (G) and Disappearance ( 0 ) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model b y proving the ability of this model t o guarantee complete stuck fault coverage an combinational and sequential circuits synthesized empl...