We propose an input protection scheme composed of thyristor devices only without using a clamp NMOS device in order to minimize the area consumed by a pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection ...

This paper studies communication networks with packet or message losses due to collisions, transmission errors and finite buffer constraints. A priori and easily computable error bounds are established for simple product form approximations. These approximations are based on ignoring and/or bounding loss probabilities. Two extreme situations are considered: (i) Networks with infinite capacities...

Gaurav Jolly and Mohamed Younis Dept. of Computer Science and Elec. Eng. University of Maryland Baltimore County 1000 Hilltop Circle Baltimore, MD 21250 [email protected] and [email protected] Abstract Networking of unattended sensors has become very attractive for many civil and military applications such as disaster management and remote surveillance. Sensors in such applications are usually e...

Initial experimental and numerical simulation results for interdigitated back contact silicon heterojunction (IBC-SHJ) solar cell, which combines the high voltage potential of heterojunction solar cells while avoiding the absorption losses and allowing high short circuit currents, are reported. Cells without intrinsic buffer layers were fabricated as a proof of concept. The cells with intrinsic...

Abstract While the first generation of silicon solar cells offers a clean and unlimited energy source, technology has matured where costs dominate, theoretical power conversion efficiency is reaching its limits. The new thin-film emerging as an affordable alternative to their bulky counterparts. much cheaper method quickly fabricate that use less material with good optical electronic properties...

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems. A digital system’s clocks must have not only low jitter, low skew, but also well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a mul...

Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits by David Anthony Papa Chair: Igor L. Markov In modern VLSI design, physical synthesis tools are primarily responsible for satisfying chip-performance constraints by invoking a broad range of circuit optimizations, such as buffer insertion, logic restructuring, gate sizing and relocation. This proc...

In an effort to eliminate the electronic bottleneck, new optical switches/routers (hardware) are being built for the next-generation optical Internet where IP runs over an all-optical WDM layer. However, important issues yet to be addressed in terms of protocols (software) are how to develop a new paradigm that does not require any buffer at the WDM layer, as in circuit switching, and eliminati...

An offset voltage adjustment technique, which can be used to reduce the offset voltage of the buffer amplifier in the liquid-crystal display signal driver, is proposed. This adjustment, which is finished before driving the display panel, does not need to be adjusted for every row scanning cycle and does not increase the settling time. An experimental prototype output buffer implemented in a 0.3...

floorplanning is an important step in physical design of vlsi circuits. it is used to plan the positions of a set of circuit modules on a chip in order to optimize the circuit performance. however, modern floorplanning takes better care of providing extra options to place dedicated modules in the hierarchical designs to align circuit blocks one by one within certain bounding box for helping seq...