A fabrication technique involving electroand electroless copper deposition was used to produce all-copper chip-to-substrate interconnects. This process electrolessly joins copper pillars, followed by annealing at 180°C. The process is tolerant to in-plane and through-plane misalignment and height variations. The mechanical compliance and electrical performance of copper-pillar chip-to-substrate...

For System-on-Chip (SoC) using deep sub-micron technologies, semiglobal and global interconnects are susceptible to crosstalk defects that may lead to mal-function and timing failures. Removal of crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage, it is necessary to understand the factors affecting this noise. In t...

We fabricate and demonstrate devices in silicon that leads towards the goal of implementing optical information processing on a silicon chip. To this effect, we demonstrate all-optical multi-level logic using a system of symmetric ring resonators in parallel. The device can form the basis of an on-chip optical digital to analog converter (ODAC). We also demonstrate ultra low cross talk by using...

In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previousl...

Multi-socket server boards (MSBs) exploit the interconnection of multiple processor chips towards forming powerful cache coherent systems, with interconnect technology comprising a key element in boosting processing performance. Here, we present an overview current electrical interconnects for MSBs, outlining main challenges currently faced. We propose use silicon photonics (SiPho) advancing th...

technology with through-silicon vias and low-volume leadfree interconnections K. Sakuma P. S. Andry C. K. Tsang S. L. Wright B. Dang C. S. Patel B. C. Webb J. Maria E. J. Sprogis S. K. Kang R. J. Polastre R. R. Horton J. U. Knickerbocker Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidt...

In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of clustering adopted in processors is to replace the centralized instruction scheduler with multiple smaller schedulers that work in parallel within a single chip. Studies have found that existing interconnects connecting ...

 More than thousand million transistors  Working frequency: multiple giga-hertz (GHz)  Power consumption increases exponentially  Capture the potential problems of power integrity  Accurate modeling and dynamic simulation of the power/ground (P/G) grid critical for VLSI circuit design and verification.  Modeling the inductive effect of on-chip and off-chip interconnects is another researc...

With many system bus alternatives in telecom, signal processing, etc, chip designers face the prospect of having to support multiple interfaces to meet interconnect requirements. Designers must then build next-generation chip architectures that deliver reliable interconnect architectures and ensure interworking between SoC heterogeneous IP blocks. In this article we show how formal verification...