The sequential element (flip-flop) is a basic building block to design any clocking system, which consists of the clock distribution tree and flip-flops. A large portion of the on chip power is consumed by the clocking system the total power consumption of the clocking system depends on both clocking distribution tree and also the register elements (flip-flops). The power consumption of registe...

In view of the inefficiency and cheating in time attendance, a face recognition attendance management system has been developed. The is developed under Windows 10 using Java language MySql database. After user logs on to system, click punch-in button. calls camera through openCV take pictures, then matches this photo with If match successful, can punch successfully. full day's work calculated b...

A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves ...

A family of keystream generators, called the LILI keystream generators, is proposed for use in stream cipher applications and the security of these generators is investigated with respect to currently known attacks. The design is simple and scalable, based on two binary linear feedback shift registers combined in a simple way, using both irregular clocking and nonlinear functions. The design pr...

Clocking considerations and the design of clocked storage elements are discussed in this paper. We present a systematic approach for deriving a clocked storage element suitable for “time borrowing” and absorption of clock uncertainties. We explain how to compare different clocked storage elements with each other, and discuss issues related to power consumption and low-power designs. Finally, re...

The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford Unversity and Texas Instruments in a 1.5V 0.15 μm process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design ...

The importance of the issue of optimizing the timing behavior of VLSI circuits probably needs no introduction to any reader of this paper, and a great deal of e ort has been invested into research in this eld. This paper considers the method of retiming [1], which proceeds by relocating ipops within a network to achieve faster clocking speeds. A novel approach to retiming that utilizes the solu...

We developed and piloted a methodology to establish TB related work load at primary care level for clinical and laboratory staff. Workload is influenced by activities to be implemented, time to perform them, their frequency and patient load. Of particular importance is the patient pathway for diagnosis and treatment and the frequency of clinic visits. Using observation with checklists, clocking...