We show transformations that convert blocking assignments into non-blocking assignments. Such transformations are useful because the parallel-processing nature of hardware is more easily conceptualized and mapped to technology with non-blocking assignment. To validate our theory, we synthesized using Synopsys FPGA Express, which supports both blocking and non-blocking assignments. Some of these...

This paper analyzes the power consumption of an array pipelined multiplier. To precisely realize a low power pipelined multiplier, the analytical model for a clocking system is presented. Simulation results show that the storage element is the key-component in a high performance pipelined multiplier macro. Compared with the conventional DFF and latch, the new low power DFF as PTTFF [6] achieves...

An aperiodic test clock methodology to reduce test time of wafer sort has been recently proposed. In practice, however, an automatic test equipment (ATE) allows only a small number of clock periods and finding those is a mathematically complex problem. This paper proposes an algorithm for optimal selection of any given number of tester clock periods. Keywords-Aperiodic clock, Test time reductio...

Recent experiments have demonstrated a working cell suitable for implementing the quantum-dot cellular automata ~QCA! paradigm. These experiments have been performed using metal-island clusters. The most promising approach to QCA operation involves quasiadiabatically switching the cells. This has been analyzed extensively in gated semiconductor cells. Here we present a metal-island cell structu...

This paper introduces an architecture for quantumdot cellular automata (QCA) systems with the potential for high throughput and low power dissipation. The combination of regions with Bennett clocking and of regions used for memory storage combines the low power advantages of reversible computing and the high throughput advantages of pipelining. A simple case study is employed to evaluate the pr...