In this paper, we present a hardware friendly binary decision tree (DT) classifier for gas identification. The DT classifier is based on an axis-parallel decision tree implemented as threshold networks—one layer of threshold logic units (TLUs) followed by a programmable binary tree implemented using combinational logic circuits. The proposed DT classifier circuit removes the need for multiplica...

In this paper, we propose a new model for directly evaluating DPA leakage from logic information in CMOS circuits. This model is based on the transition probability for each gate, and is naturally applicable to various actual devices for simulating power analysis. We also report on our study of the effects of the previously known countermeasures on both our model and FPGA, and show the possibil...

In combinatorial blocks of static CMOS circuits transistor sizing can be applied for delay balancing as to guarantee synchronously arriving signal slopes at the input of logic gates, thereby avoiding glitches. Since the delay of logic gates depends directly on transistor sizes, their variation allows to equalize different path delays without influencing the total delay of the circuit. Unfortuna...

ICID (Integrated Circuit IDentification) is a small mixed-signal cell that can be added to the test logic on a CMOS integrated circuit. It provides a unique 224 bit identification number that can be accessed during die test. This identification can be used to correlate test information for individual die on the wafer, through package test, and into the field and back. The identification bits ar...

Keywords: Low-power Adiabatic logic Energy recovery Multiplier a b s t r a c t As the density and operating speed of complementary metal oxide semiconductor (CMOS) circuits increases, dynamic power dissipation has become a critical concern in the design and development—of personal information systems and large computers. The reduction of supply voltage, node capacitance, and switching activity ...

Noise issues are becoming a main concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem in this paper we present a new noisetolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. Simulation results for CMOS AND gate show that the proposed technique has an improvement in the ANTE of 3.4 over convention...

Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrier e ects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design phase. The electromigration and the hot carier e ects are estimated at the gate level using signal activi...

This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiplevalued current-mode circuit technology for high-density lowpower implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circu...

Power optimization is the major problem in digital circuit design. In this paper using MTCMOS and stack techniques are proposed. Multi threshold CMOS sleep stack and logic stack, super cutoff sleep stack and logic stack are proposed. Stacking is introduced in MTCMOS concept which decreases leakage power based on the power dissipation of pMOS and nMO Stransistor. MTCMOS technique uses multiple v...

In this paper a single-cycle issue queue circuit architecture that simplifies the wakeup and selection logic is proposed. The micro-architecture and fully static CMOS circuits are presented for a 32-entry queue that issues four instructions per cycle. The instruction-ready signals are divided into groups and processed in parallel to issue the four oldest ready instructions. The complete issue q...