A low-power, high-gain CMOS low noise amplifier (LNA) for use as the first stage of a subsampling receiver is proposed. The performance of +96-dB voltage gain and less than 1-dB Noise Figure (NF) with very low power consumption is reported for the first time and makes it suitable for subsampling mixer with Track and Hold (T/H) circuit. The LNA contains both tuned and inductorless amplifier stag...

This paper presents design concept of Operational Transconductance Amplifier (OTA). The 0.18μm CMOS process is used for Design and Simulation of this OTA. This OTA having a bias voltage 1.8 with supply voltage 1.8 V. The design and Simulation of this OTA is done using CADENCE Spectere environment with UMC 0.18μm technology file. The Simulation results of this OTA shows that the open loop gain o...

This paper presents design concept of Operational Transconductance Amplifier (OTA). The 0.18μm CMOS process is used for design and simulation of this OTA. This OTA having a biasing current of 15.6 μA with supply voltage ±1.25 V. The design and simulation of this OTA is done using CADENCE Spectre environment with UMC 0.18 μm technology file. The simulation results of this OTA shows that the open...

−A 300MHz CMOS seventh−order linear phase gm−C filter based on a current−mode multiple loop feedback (MLF) leap−frog (LF) structure is realized. The filter is implemented using a fully−differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18μm CMOS process with 2.5V power supply have shown that the cu...

This paper presents a new common-mode stabilization method for a CMOS differential cascode Class-E power amplifier with LCtank based driver stage. The stabilization method is based on the identification of the poles and zeros of the closed-loop transfer function at a critical node. By adding a series resistor at the common-gate node of the cascode transistor, the right-half-plane poles are move...

..-htracf —A high-speed CMOS comparator has been designed and fabricated using a standard 3pm process. A dynamic latch preceded by an offset-cancelled amplifier is used to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADC’S) can be built with this comparator. The use of pipefining within ...

This paper presents a Class-D power amplifier for bandpass pulse width modulated (BP-PWM) and bandpass deltasigma modulated (BP-DSM) signals at 20 MHz. A 1-bit 6-th order topology is used in the ∆Σ-modulator. Integral noise shaping is used in the generation of the bandpass pulse width modulated signal. A two sided pulse width modulation is used with a 6-bit 4th-order noise shaper. The push-pull...

The layout design of hysteresis controlled switching-mode amplifier for fourth generation Long-Term Evolution (4G LTE) applications is presented in this paper. Those circuits are used in envelope amplifiers (EAs) architectures, which supply voltage to the transmitter’s power amplifier (PA). The proper layout design can help to improve the overall efficiency of EA, because most of the energy del...

The low noise amplifier (LNA) serves as the first component of the radio frequency receiver system. The performance of LNA determines the sensitivity and selectivity of the receiver. In order to maximize performance the gain, noise figure and input matching of LNA needs to be optmized. This paper presents a 60GHz low noise amplifier on 0.13-μm standard CMOS technology designed using classical n...

A three-stage V-band amplifier implemented in 65-nm baseline CMOS technology is presented in this paper. Slow-wave coplanar waveguides are used for matching and interconnects to study the benefits of using this line type in amplifier design. Measured power gain, noise figure and 1 dB output compression point at 60 GHz are 13 dB, 6.3 dB and ?4 dBm, respectively. The amplifier has 19.6 GHz of 3 d...