We have developed a highly parallel computer with distributed memory called the AP1000. The system consists of 64 to 1024 processing elements and three independent networks called Torus network (T-net), Broadcast network (B-net), and Synchronization network (S-net). The design goal for the AP1000 is to attain low latency, high throughput communication. To reduce the overall communication latenc...

Master thesis regulations [10] Clarification for students on delivery of the PhD report: The student has to contact each member of the examination panel and deliver him a copy (all or at least one of the copies in paper for the record/library) ONE week before the defence. You don't need to contact the DAC admin or FIB for this. A few days after the defence you can contact FIB (academic office) ...

The discrete–event simulation language Pearl, which is specifically designed for simulating computer architectures, features a strong statistical analysis engine. However, the output of this engine is text–based and postmortem. In this paper, we introduce a flexible graphical user interface support library for Pearl, addressing the runtime visualization of computer architecture simulations. The...

In recent years, advances in computer architecture have slowed dramatically with most simulation results demonstrating only incremental architectural innovation. This is further exacerbated by increased processor and system complexity spurred by a seemingly unlimited number of transistors at computer architect’s disposal. Computer architects produce a myopic view of their systems through the le...

Vedic mathematics or ancient mathematics is a unique technique of calculations based on 16 sutras. It provides an innovative way of computation of almost all the mathematical operations. In this era of digitization, engineers are working on increase speed of the digital circuits while reducing the size and power consumed. Arithmetic operations are the basic units of all the digital circuitry an...

Master thesis regulations [10] Clarification for students on delivery of the PhD report: The student has to contact each member of the examination panel and deliver him a copy (all or at least one of the copies in paper for the record/library) ONE week before the defence. You don't need to contact the DAC admin or FIB for this. A few days after the defence you can contact FIB (academic office) ...

The past few years has seen a sea change in computer architecture that will impact every facet of our society as every electronic device from cell phone to supercomputer will need to confront parallelism of unprecedented scale. Whereas the conventional multicore approach (2, 4, and even 8 cores) adopted by the computing industry will eventually hit a performance plateau, the highest performance...

.......A year ago, the 36th International Symposium on Computer Architecture featured the latest installment of the Computer Architecture Research Directions workshop. CARD is a series of minipanels, in which two experts take somewhat opposing viewpoints on important topics related to the future of computer architecture, under the direction of a moderator. As in previous years, attendees flocke...

This paper presents SiMR, a simulator of the Rudimentary Machine designed to be used in a first course of computer architecture of Software Engineering and Computer Engineering programmes. The Rudimentary Machine contains all the basic elements in a RISC computer, and SiMR allows editing, assembling and executing programmes for this processor. SiMR is used at the Universitat Oberta de Catalunya...