Abstract This paper reports on the fabrication and characterization of high quality factor (Q) copper (Cu) inductors with thick insulator on standard silicon (Si) substrate (ρ = 10–20 cm). The thickness and the area of the insulating layer are optimized for high Q by fabricating inductors on very thick (∼50 μm) embedded silicon dioxide (SiO2) islands and 4–20 μm thick PECVD SiO2 coated standard...

This paper presents an energy-harvesting system consisting of amorphous-silicon (a-Si) solar cells and thinfilm-transistor (TFT) power circuits on plastic. Along with patterned planar inductors, the TFTs realize an LCoscillator that provides power inversion of the DC solarmodule output, enabling a low-cost sheet for inductivelycoupled wireless charging of devices. Despite the low performance of...

Symmetric spiral inductors are used for differential circuit applications for their robustness and superior noise rejection properties. In this work, characteristics of quality factor and inductance of symmetric inductors having octagonal structures, and the methods to improve performance have been suggested using the Agilent Momentum simulator [1]. From the results, we get differential quality...

This paper proposes an optimization methodology of on-chip spiral inductors. Characteristics of spiral inductors heavily depend on layout structures. We then formulate the characteristics with structural parameters and frequency as variables using a response surface method. The proposed method uses S-parameters to express inductor characteristics, and hence our method is independent of spiral g...

In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.32Ω for a control current of 120μA. In order to r...

In this work, we present new topologies for realizing one lossless grounded inductor and two floating, one lossless and one lossy, inductors employing a single differential difference current conveyor (DDCC) and a minimum number of passive components, two resistors, and one grounded capacitor. The floating inductors are based on ordinary dual-output differential difference current conveyor (DO-...

This article gives a simple set of rules for the design of integrated inductors with a good quality factor in a standard CMOS process. This guide takes into account almost all the degrees of freedom that a designer has when creating an inductor: the number of sides, the number of metal layers, the center hole, the external radius, metal width and spacing. To verify these rules, a set of inducto...

CMOS implementations for RF applications often employ technology modifications to reduce the silicon substrate loss at high frequencies. The most common techniques include the use of a high-resistivity substrate (ρ>10Ω-cm) or silicon-on-insulator (SOI) substrate and precise bondwire inductors [1, 2]. However, these techniques are incompatible with low-cost CMOS manufacture. This design demonstr...