We assume a link-register communication model under read/write atomicity, where every process can read from but cannot write into its neighbours’ registers. The paper presents two self-stabilizing protocols for basic fair and reliable link communication primitives. The first primitive guarantees that any process writes a new value in its register(s) only after all its neighbours have read the p...

Intel’s processor clock has tocked, delivering a nextgeneration architecture for PCs and servers. At the recent Intel Developer’s Forum (IDF), the company unveiled its Sandy Bridge processor architecture, the next tock in its tick-tock roadmap. The new CPU is an evolutionary improvement over its predecessor, Nehalem, tweaking the branch predictor, register renaming, and instruction decoding. Th...

A balanced increase of memory bandwidth and computational performance is one of the current trends towards high performance microprocessors. This improvement can be attained either by replicating resources such as buses and functional units or by making them more complex. For example, some microprocessors, as the IBM’s POWER2 double the width of the buses between the register file and the first...

A register file is a critical resource of modern processors. Most hardware and software mechanisms to manage registers across procedure calls do not efficiently support multithreaded programs. To switch between parallel threads, a conventional processor must spill and reload thread contexts from registers to memory. If context switches are frequent and unpredictable, a large fraction of executi...

The design of high-performance value communication structures represents a significant challenge in the implementation of future microprocessors. The complexity of these structures— namely, the register file, the bypass network, and the instruction window—dwarfs that of the actual instruction execution hardware and has become the predominant factor in determining the maximum operating frequency...