IDDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios, in which the ratio of maximum to minimum IDDQ is used to screen faulty chips, has been previously proposed. At the wafer level neighboring chips have similar fault-free properties and are correlated. In this paper, use of spatial correlat...

In the deep sub-micron regime, the performance of network-on-chip (NoC) architectures is bound by the limited power and area budget. Proposed is a low-power low-area NoC architecture using a novel power-efficient control circuit that enables repeaters along the interrouter links to function as adaptive link buffers, thereby reducing the number of buffers required in the router. Simulation resul...

Design of low power, higher performance digital signal processing elements are the major requirements in ultra deep sub-micron technology. This paper presents an IEEE-754 standard compatible single precision Floating-point Computation SHaring Multiplier (FCSHM) scheme suitable for low-power and high-speed signal processing applications. The floating-point multiplier used at the filter taps effe...

Carbon based nanomaterials such as metallic single walled carbon nanotubes (SWNT), multi-wall carbon nanotubes (MWNT), and graphene have been considered as some of the most promising candiadates for future interconnect technology. In current deep sub-micron level technology, MWNTs have potentially provided an attractive solution over SWNT bundles. This paper presents a comprehensive analysis of...

VLSI physical design automation plays a vital role as we move to deep sub-micron designs below 0.18 microns. Power dissipation, performance and area are dominated by interconnections between elements in the circuit under consideration. Global Placement followed by iterative improvement placement (detailed placement) is the most robust, simple and successful approach in solving the placement pro...

With recent promising progress on nanoscale devices including semiconductor nanowires and nanowire crossbars, researchers are trying to explore the possibility of building nanoscale computing systems. We have designed a nanoscale application-specific architecture called NASIC, which is based on semiconductor nanowire grids and FETs at crosspoints. In this paper, we propose a built-in redundancy...

his article presents a comprehensive analysis of the thermal effects in advanced high-performance interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge (ESD). Technology (Cu, low-k, etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration (EM) reliability, have been analyzed simult...

We report on the formation of organized sub-micron YBa(2)Cu(3)O(7) (YBCO) dots induced by irradiating femtosecond laser pulses on YBCO films prepared by pulse laser deposition with fluence in the range of 0.21 approximately 0.53 J/cm(2). The morphology of the YBCO film surface depends strongly on the laser fluences irradiated. At lower laser fluence (approximately 0.21 J/cm(2)) the morphology w...

Rohit Kapur Thomas W. Williams Synopsys Inc. P lay the word association game with electronics, and the first words that come to mind might be “inexpensive” and “reliable.” Everyone expects electronic items to become continually less expensive and quickly outdated. We also expect them to work when we bring them home. Do any of us ever question how and why this happens? A large part of the answer...

Since 2003, we use the GSI heavy-ion microprobe to irradiate living cells with ions from the UNILAC [1]. Two specific properties of the microbeam method make it stand out among other, more conventional irradiation procedures: First, we precisely control the dose by counting and switching individual particles that are to be delivered to the target, down to the low-dose limit of a single ion per ...