It is well known that in deep submicron technologies the coupling capacitance between adjacent wires is a critical portion of the total wire capacitance, while at the same time the capacitance between wire and substrate has become the fringing component. High frequency signals travelling across multiple level interconnect structures generate proximity effects, i.e. crosstalk effects, between ad...

The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-submicron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the existing dual-bit-line architecture. The...

0740-7475/02/$17.00 © 2002 IEEE September–October 2002 CMOS IC SCALING increases device/interconnect density to allow more logic on a die at higher clock rates, enhancing overall performance. Improvements in process technology enable integration on a single die of circuits with different functions that require distinct manufacturing process steps. With added constraints of reduced time to marke...