The problems of delay-dependent robust stability and stabilization of a class of uncertain, linear discrete-time singular systems with state-delay are examined. The parametric uncertainties are assumed to be time-invariant and normbounded appearing in the state and delay matrices. A new system representation is developed to derive new delay-dependent stability criteria without relying on overbo...

A new delay-dependent criterion is developed for robust stability of linear discrete-time singular systems with state-delay and parametric uncertainties. The time-delay is varying between known bounds and the uncertainties are assumed to be time-invariant and norm-bounded appearing in the state and delay matrices. The new criterion is achieved by an expanded state-space system representation. A...

the modulation response, relative intensity noise and frequency noise characteristics of qd lasers are investigated theoretically, in presence of an additional optical pumping. it is revealed that the modulation response of qd laser enhances under additional optical beam. by small signal analysis of the carriers' and photons' rates, it is proposed that by injecting excess carriers to ...

We characterize the stability conditions with an arbitrary statedependent time-varying round-trip delay in the context of single-flow and singleresource for Kelly’s optimization based rate control scheme using invariance techniques. It is shown that the stability conditions with an arbitrary fixed delay are sufficient for the stability of the system with a state-dependent time-varying delay.

Fault recovery techniques must be reexamined in the light of the new guaranteed performance services that networks will support. We investigate the rerouting of guaranteed performance service connections on the occurrence of link faults, focussing on the aspects of route selection and establishment in the network. In a previous investigation, we explored some components of rerouting in the pres...

A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 μ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold times of I/O registers or buffers. The frequency lock range of the DLL is 150-600 MHz (4x). The DLL uses a combined phase detector and charge pump circuit (PD+CP) for increased speed and reduced jitter. The DLL also em...