نتایج جستجو برای: depth chip level

تعداد نتایج: 1264735  

Journal: :journal of modern processes in manufacturing and production 2015
hassan gheisari ebrahim karamian

most of the materials used in the industry of aero-engine components generally consist of titaniumalloys. advanced materials, because of their excellent combination of high specific strength, lightweight and general corrosion resistance. in fact, chemical wear resistance of aero-engine alloyprovides a serious challenge for cutting tool material during the machining process. the reductionin cutt...

2000
Voicu Popescu Anselmo Lastra John Eyles

Rendering from images with depth (Image-Based Rendering by Warping, IBRW) is an appealing 3D-computer-graphics technique since it alleviates the modeling bottleneck and promises photorealism at interactive rates. Current, and probably near future silicon technology cannot produce single-chip IBRW renderers that are powerful enough. Thus a high-level parallelism scheme needs to be employed that ...

2001
Bart Vermeulen Steven Oostdijk Frank Bouwman

Decreasing feature sizes and increasing customer demand for more functionality have forced design teams to re-use design blocks and application platforms. As a result, re-use of test, design-for-test and design-for-debug for large system chips is becoming increasingly important and increasingly necessary. In this paper, the test and debug features of the Nexperia PNX8525 chip are presented. The...

Journal: :IEICE Electronic Express 2014
Baigen Cai Cheng-ming Jin Lian-chuan Ma Yuan Cao Hideo Nakamura

IEC 61508-2010 puts special limits on the on-chip redundancy of one single chip, for example the safety integrity level (SIL) is limited up to SIL 3. About this, however, there are no specific explanations. Based on the safety-critical system of on-chip redundancy for a typical programmable logic device (FPGA), this paper proves that the highest SIL is 3; analyses the factors that may impact th...

1997
Mike Wessler Lynn Andrea Stein

We present an active vision head-eye system that mimics the low-level visual reflexes of an infant. The software architecture is fast and robust, consisting of very simple modules that interact to correct each other’s errors. The system produces stable output and is designed to be the base framework of a more complete visual system. It tracks objects at 30 Hz with smooth motion, running on a si...

2008
Yun Shuai Ansuman Banerjee David Klotzkin Ian Papautsky

In this paper, we present an improved high-sensitivity approach for on-chip fluorescence-based measurements for disposable lab-on-a-chip (LOC). We use a bilayer organic photodiode (OPD), cross-polarization, and improved integration to enhance Rhodamine 6G limit of detection (LOD) to 10 nM, which is a 10-100 fold improvement over current reports in literature. A prototype system was fully charac...

1996
Wang-Dauh Tseng Kuochen Wang

In this paper, we present a novel and efticient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method and the smart substrate to provide two levels at speed test. The IEEE 1149.1 boundary scan standard is used to ofSer the necessity of controllability and observability. Part of the boundary scan cells used in the chip le...

2009
K. Tatas

This paper presents a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA implementation figures are given for various implementation parameters of the Network Interface Element, demonstrating the performance/area trade-off of 3D NoC archi...

2011
Jae Gon Kim Jong Hak Kim Hun Ho Ham Jueng Hun Kim Chan Oh Park Soon Suk Park Jun-Dong Cho

In this paper, we propose a real-time virtual reconvergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth postprocessing, and virtual view control, is implemented in 60 fps on a single Xilinx Virtex-5 FPGA chip.

Journal: :IBM Journal of Research and Development 2013
IBM Blue Gene team

The heart of a Blue GeneA/Q system is the Blue Gene/Q Compute (BQC) chip, which combines processors, memory, and communication functions on a single chip. The Blue Gene/Q Compute chip has 16 þ 1 þ 1 processor cores, each with a quad single-instruction, multiple-data (SIMD) floating-point unit, and a multi-versioned Level 2 cache that provides hardware support for transactional memory, speculati...

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