Design of a high performance and high-density multiplier is presented. This multiplier is constructed by using the Wallace tree structure with pipelining. A fast carry select adder is used for the final two-operand adder. It is shown that the time delay for the entire multiplier is O(log(n)). The design is particularly carried out for a 32-bit multiplier with two sections of pipelining, to bala...

A design of high performance 64 bit Multiplier-andAccumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder. The total design is coded with Synthesize and simulate by verilog-HDL.

Many Digital Signal Processing (DSP) algorithms use floating-point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal of every VLSI designer. This paper presents a comparison of pipelined floating-point adder complaint with IEEE 754 format with an unpipelined adder also compl...

Adders are very often in the critical path of a computer, so it is very important that their performance will not limit the cycle time of the machine. In VLSI applications, area and power are also important factors which must be taken into account in the design of a fast adder. One choice is the carry-skip adder, which because of its great topological regularity and layout simplicity is conside...

Sub-threshold is a new paradigm in the digital VLSI design today. In Sub-threshold region, transistors are operated in sub-threshold voltage. This paper examine the Carry Look Ahead (CLA) Adder with dual mode logic (DML)principle, in which gates are operated in sub-threshold regime and comparison of results with Conventional basic Carry look ahead adder . The number of gates in CLA is 5 includi...

We present a self-contained and detailed description of the parallel-prefix adder of Ladner and Fischer. Very little background is assumed in digital hardware design. The goal is to understand the rational behind the design of this adder and view the parallel-prefix adder as an outcome of a general method. This essay is from the book: Shimon Even Festschrift, edited by Goldreich, Rosenberg, and...

Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is b...

In this paper we show how case-based reasoning techniques can be used to extract and reuse solutions previously found by a heuristic (a genetic algorithm in our case) used to solve problems in a specific domain (MSI and SSI combinational circuit design). This reuse of partially built solutions allows us to improve convergence time of our heuristic since the building blocks of the “good" solutio...

In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper proposes a new 4 * 4 reversible gate called “TSG” gate. The proposed gate is used to design efficient adder units. The most significant ...