Adder is an important functional unit of a computer. This paper provides design of a low delay threshold adder (LDTA) using fan-in bounded gates in nanotechnology. An n-bit LDTA with a fan-in bound of M + 1 has delay of O(log(N/M)) and hardware complexity of O(N log(N/M)). This design strategy allows a trade-off between the fan-in bound, delay and the complexity.

It is shown that in a standard discrete neural network model with small fan-in, tolerance to random malicious faults can be achieved with a log-linear increase in the number of neurons and a constant factor increase in parallel time, provided fan-in can increase arbitrarily. A similar result is obtained for a nonstandard but closely related model with no restriction on fan-in.

A vertical axis wind turbine (VAWT) was positioned at the discharge outlet of a cooling tower electricity generator. To avoid a negative impact on the performance of the cooling tower and to optimize the turbine performance, the determination of the VAWT position in the discharge wind stream was conducted by experiment. The preferable VAWT position is where the higher wind velocity matches the ...

Feature indexing techniques are promising for object recognition since they can quickly reduce the set of possible matches for a set of image features. This work exploits another property of such techniques. They have inherently parallel structure and connectionist network formulations are easy to develop. Once indexing has been performed, a voting scheme such as geometric hashing [10] can be u...

I consider a topographic projection between two neuronal layers with different densities of neurons. Given the number of output neurons connected to each input neuron (divergence or fan-out) and the number of input neurons synapsing on each output neuron (convergence or fan-in) I determine the widths of axonal and dendritic arbors which minimize the total volume ofaxons and dendrites. My analyt...

Backpropagation learning algorithms typically collapse the network’s structure into a single vector of weight parameters to be optimized. We suggest that their performance may be improved by utilizing the structural information instead of discarding it, and introduce a framework for “tempering” each weight accordingly. In the tempering model, activation and error signals are treated as approxim...

A fan-out wafer level package (FOWLP) with double-sided four redistribution layers (RDLs) and the mega pillars connecting front back RDLs has been proposed for millimeter-wave applications. well-matched package-board transition designed in this paper. The simulated insertion loss is about 0.82 dB at 79 GHz, return better than 10 from 72 GHz to 86 GHz. More importantly, two different measurement...

OBJECTIVE To examine the relation between room ventilation during sleep and risk of sudden infant death syndrome (SIDS). DESIGN Population-based case-control study. SETTING Eleven California counties. PARTICIPANTS Mothers of 185 infants with a confirmed SIDS diagnosis and 312 randomly selected infants matched on county of residence, maternal race/ethnicity, and age. Intervention Fan use a...

The present paper introduces the new interconnection network of the BOPS ManArray family of available core products. To form a ManArray network, the processing elements are completely connected within clusters and communicate with members of only two other clusters thereby reducing signal fan-out and wiring density. With this simple network, single-step communications between a hypercube and it...