Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. Now a days, there are an increasing number of portable applications requiring small-area, low power and high throughput circuitry. The circuits with low power consumption become the major issu...

Compressor trees are efficient circuits to realize multi-operand addition with fast carry-save arithmetic. They can be found in various arithmetic applications like multiplication, squaring and the evaluation of polynomials with application to function approximation. Finding good elementary compressing elements on FPGAs is a non-trivial task as an efficient mapping to look-up tables and carry-c...

This paper presents a methodology for improving the speed of high-speed adders. As a starting point, a previously proposed method, called "speculative completion," is used in which fast-terminating additions are automatically detected. Unlike the previous design, the method proposed in this paper is able to adapt dynamically to (1) application-specific behavior and (2) to adder-specific behavio...

In this paper, a novel quantum-dot cellular automata (QCA) adder design is presented that reduces the number of QCA cells compared to previously reported designs. The proposed one-bit QCA adder structure is based on a new algorithm that requires only three majority gates and two inverters for the QCA addition. By connecting n one-bit QCA adders, we can obtain an n-bit carry look-ahead adder wit...

This paper presents a novel approach for theoretical estimation of power consumption in digital binary adders. Closed-form expressions for power consumption of four different types of binary adders – the ripple-carry adder, the Manchester adder, a multiplexor-based carry-select adder and an efficient tree-based look-ahead adder – are derived in terms of word-length and pre-computed technologysp...

A power-efficient 8-bits digital adder using the new arithmetic A2 redundant binary representation is presented. This structure is very suitable for implementation in VLSI of mixed-signal circuits built around Multiplier Digital to Analog Converter (MDAC) cells. Using a reduced transistor count Full-Adder cells shows that our approach significantly reduces the power consumption of such adders c...

Processor speed largely governed by the multiplier architectures. It is desired to have faster ALU with lower power consumption for portable applications to have good battery life. Hence, there is need to address different multiplier architectures. In this paper, the analysis of 4-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) and conventional multiplier with two different ...

In this paper a new area efficient, high-speed and ultra-low power 1-bit full adder cell is presented. The performance: power, time delay and power delay product (PDP) of the proposed adder cell has been analyzed in comparison with the four existent low-power, high-speed adders. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology and intensive simul...

Reversible quantum computer is gaining interest for the future computer system. With the advent of quantum computer and reversible logic, design and implementation of all devices has received more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. The research objective is to increase speed of operation for addition of BCD numbers while minimizing the ...

In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency....