With the Gottesman-Kitaev-Preskill (GKP) encoding, Clifford gates and error correction can be carried out using simple Gaussian operations. Still, non-Clifford gates, required for universality, require non-Gaussian elements. In their original proposal, GKP suggested a particularly method of single application cubic phase gate to perform logical $T$ gate. Here we show that this approach performs...

Integrated circuit design is entering an era of truly nanoscale transistors with minimum device geometries now at 32nm and soon to be at 25nm. While actual transistor and logic gate sizes are many times the minimum lengths possible, logic elements are becoming increasingly small and more closely packed together. There is now an increasing possibility of getting coupling errors where nearby logi...

Genetic Algorithm based automatic evolution of fault tolerant digital circuits has been examined at three different levels. At the first level, multiple working designs are automatically generated, offline, without additional human design effort and each is documented with the unused resources information. This information is used for fault tolerance. Depending on the number of versions generat...

This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K to 800K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST controller for at-speed testing. Compar...

Traditional fault tree analysis is not always sufficient when analysing complex systems. To overcome the limitations dynamic fault tree (DFT) analysis is suggested in the literature as well as different approaches for how to solve DFTs. For added value in fault tree analysis, approximate DFT calculations based on a Markovian approach are presented and evaluated here. The approximate DFT calcula...

With the increasing demand for highly dependable and constantly available systems, being able to reason about faults and their impact on systems is gaining considerable attention. In this paper, we are concerned with the provision of a logic especially tailored for describing fault tolerance properties, and supporting automated verification. This logic, which we refer to as dCTL, employs tempor...

By increasing, the complexity of chips and the need to integrating more components into a chip has made network –on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tol...

Reversible logic is one of the emerging fields of research in the areas of low power computation, Optical information processing, Fault tolerant system, bio information, quantum computation and nanotechnology. ALU is the most vital component of any processing system and need to consume as much less energy as possible in the mean while must be resistant to faults. In this paper the design of a f...