We present early results from a 4×4 2.4GHz ISM band multiple-input multiple-output (MIMO) testbed developed at the University of Newcastle for over-the-air evaluation of MIMO algorithms. To provide maximum flexibility for development of 3GPP Long Term Evolution (LTE) algorithms, the testbed is designed around a field-programmable gate array (FPGA). The testbed features a simple GUI interface fo...

In order to enable the non-cooperative rendezvous, capture, and removal of large space debris, automatic recognition of the target is needed. Video-based techniques are the most suitable in the strict context of space missions, where low-energy consumption is fundamental, and sensors should be passive in order to avoid any possible damage to external objects as well as to the chaser satellite. ...

With the XC6200 FPGA Xilinx introduced the first commercially available FPGA designed for reconfigurable computing. It has a completely new internal architecture, so new design algorithms and software is needed. Due to the fact that most applications are in the research area, the number of sold units seems to be small. Because of this progress of design tools for this architecture is rather low...

In this work the problem of modeling reconfigurable systems behavior with a precise, executable semantics is considered. The possibility of synthesising such models onto reconfigurable technologies is also faced. The modeling problem is tackled with the definition of a formalism based on the possibility of Java to vary its class pool at run-time. Feasibility of the sinthesis approach is verifie...

Enhancing undergraduate and graduate curriculum to include state-of-the-art tools and techniques deserves utmost importance in this fast pacedworld of engine ering and technological growth. Design, the art of applying one's knowledge and exp erienc e to the solution of real problems is what makes engineering an exciting and rewarding career. In this pap er,exp erience from teaching a senior lev...

Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice for fast prototyping and for products whose time to market is relatively short. Testing FPGAs before programming them is thus becoming a major concern to the manufacturers as well as the users. In this paper we propose a universal test for the interconnects of typical dynamic reconfigurable FPGAs. The proposed test config...

This paper deals with the mapping of loop programs onto processor arrays either implemented in an FPGA or available as (reconfigurable) coarse-grained processor architectures. Usually the proportion of processing elements to I/O-interfaces is much higher whereby problems of data transportation and synchronization are arising. In this realm, we propose a systematic approach in order to feed-out ...