Multi-gate transistors are considered to be the ultimate device concept for use in future CMOS generations. The so-called FinFET [1] is a variant with a straightforward process flow [2]. A three-dimensional sketch of the FinFET can be seen in Fig.1. The small channels benefit from superior electrostatic channel control, resulting in enhanced turn-off behavior. However, its fabrication demands e...

An all-digital full-entropy True Random Number Generator (TRNG) with measured 1.3GHz operation and total power consumption of 1.5mW at 0.75V, 25oC is fabricated in 14nm FinFET CMOS. Three independent selfcalibrating entropy sources, coupled with pre-extraction correlation suppressors and a real-time BIW extractor enable ultra-low energy consumption of 3pJ/bit, while generating cryptographic-qua...

Invention of Transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key to the development of nano electronics technology. This paper offers a brief review of some of the most popular MOSFET structure designs. The scaling down of planar bulk MOSFET proposed by the Moore’s Law has been saturated due to short channel effects a...

This paper discusses the problem of thermal coupling in many-core processors manufactured in nonplanar FinFET technologies. Our work focuses on two research goals. Firstly, the results obtained from the thermal simulations allow the investigation of mutual thermal influence between neighboring cores in such processors, what can be used to develop thermal models of such architectures. Secondly, ...

The effect of gate – drain/source underlap ( Lun ) on a narrow band LNA performance has been studied , in 30 nm FinFET using device and mixed mode simulations. Studies are done by maintaining and not maintaining the leakage current (Ioff) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used...

This paper describes the design of a 1024-core processor chip in 16nm FinFet technology. The chip (“EpiphanyV”) contains an array of 1024 64-bit RISC processors, 64MB of on-chip SRAM, three 136-bit wide mesh Networks-On-Chip, and 1024 programmable IO pins. The chip has taped out and is being manufactured by TSMC. This research was developed with funding from the Defense Advanced Research Projec...

We present a comprehensive computational toolset for low-field mobility modeling in nano-scaled SOI channels. The dimension-independent methodology allows us to treat planar devices (MOS, UTB) and non-planar ones (Bulk/SOI-FinFET, Nanowire-FET) on equal footing. The method involves combining a selfconsistent Schrödinger-Poisson solution in the channel cross-section with a linearized Boltzmann t...

The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, ...

An analytical modeling framework for quantum ballistic charge transport in the subthreshold regime, and a quantum threshold voltage model for nanoscale double-gate (DG) FinFET are presented. For subthreshold conditions, we assume that the electrostatics of the lightly doped silicon body is dominated by the inter-electrode capacitive coupling between the body electrodes. Hence, the charge is neg...