A new method is presented for transforming (m0 I nO) jntegrals to (nb I@) integrals eff55cntly. A key feature of the new ag preach is the optimization of the total number of memory operations (mops) rather than floating-point operations (flops). Solutions to the inherent tree-search pmblem were obtained which are radically different than those following when flops are taken as the cost function...

Multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All the building blocks of the proposed reconfigurable multiplier can either work as independent smallerprecision multipliers or work in ...

The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fracti...

The authors introduce two low-cost, modular, totally self checking (TSC), edge triggered and error propagating (code disjoint) flip-flops: one, a D flip-flop used in TSC and strongly fault secure (SFS) synchronous circuits with two-rail codes, the other a T flip-flop, used in a similar way as the D flip-flop but retaining the error as an indicator until the next presetting, to aid error propaga...

This paper proposes two parallelized radix-4 scalable Montgomery multiplier implementations. The designs do not require precomputed hard multiples of the operands, but instead uses Booth encoding to compute products. The designs use a novel method for propagating the sign bits for negative partial products. The first design right shifts operands to reduce critical path length when using Booth e...

Power reduction has become a vital design goal for sophisticated design applications, whether mobile or not. dropping power consumption in design enables better, cheaper products to be designed and power-related chip failures to be minimized. Researchers have shown that multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-fl...

The development of ANUPAM supercomputer systems based on parallel processing techniques has been the most outstanding achievement of Computer Division, BARC. ANUPAM Pentium III/16, is the latest and fastest supercomputer developed in April 2000, using 16 Pentium III @ 550 MHz. personal computers as compute nodes. This supercomputer is having a sustained speed of 3.5 Giga Flops, which is 2-3 tim...