This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in the behavioral description of a computation in such a way that the requirements for two important components of the final implementation cost, the number of registers and the number of interconnects, are significantly reduced. Moreover, it is shown how hot potato techni...

Transformational design is a formal technique directed at design correctness. It integrates design and veriJication by the use of pre-proven behaviour preserving transformations as design steps. A formal framework is necessary but hidden fo r the designer. Five formal aspects are integrated in the presented formal framework that is aimed at the design of complex systems composed out of differen...

Composing of multi-pole models and simulation of dynamic responses of a technical chain system is considered in the paper. Part 1 of the paper discusses difficulties arising in using existing simulation tools. A methodology is proposed that seems to be free of most of these disadvantages. Modeling of electro-hydraulic servovalve is considered as an example of chain system. An intelligent simula...

This article describes the embedding of high level synthesis algorithms in HOL. For given standard synthesis steps, we describe, how its data can be mapped to terms in HOL and the synthesis process be expressed by means of a logical derivation. In contrast to post-synthesis ver-iication techniques our approach is constructive in a sense that the proof is derived during synthesis rather than \gu...

The synthesis of dynamically recon gurable systems poses some new challenges for high-level synthesis tools. In this paper, we deal with the task of module allocation as this step has a direct in uence on the performance of the dynamically recon gurable design. We propose a con guration bundling driven module allocation technique that can be used for component clustering. The basic idea is to g...

Fault-tolerance increases hardware reliability of a VLSI design but it also has the disadvantage of increasing chip area. This area overhead can however be minimized by consideration of fault-tolerance during the high-level synthesis stage of design. We introduce an intertwined scheduling and binding algorithm for self-recovering fault-tolerant designs. Two copies in a self-recovering design ha...

This paper describes a new high-level synthesis system based on the hierarchical Production-Based Specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables and that the designer does not describe a particular form of implementation. The production-based specification also separates the ...

Data Types and High-Level Synthesis Gregory S. Whitcomb A. Richard Newton Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Berkeley, CA, 94720

For FPGA based coprocessors for elliptic curve cryptography, a significant performance gain can be achieved when hybrid coordinates are used to represent points on the elliptic curve. We provide a new area/performance tradeoff analysis of different hybrid representations over fields of characteristic two. Moreover, we present a new generic cryptoprocessor architecture that can be adapted to var...

On-line testability is essential in designs with high reliability requirements. High-level synthesis reduces time-to-market and enables efficient design space exploration. In our work, we implement on-line testable designs in a high-level synthesis environment. We refer to our new technique (inversion testing) and exploit its features, in an attempt to reduce hardware penalties. Further, we enh...