 Despite the evolution of high speed communication network to accommodate an increasingly number of applications with diverse service requirements, there still exist a number of barriers related to the deployment of the encoded video over the ATM network. In fact, additional works have to be devoted to improve protocol architecture and to guarantee the QoS. In this paper, we first analyze the ...

This paper describes work in progress to develop a standard for interoperability among high-performance scientific components. This research stems from growing recognition that the scientific community needs to better manage the complexity of multidisciplinary simulations and better address scalable performance issues on parallel and distributed architectures. Driving forces are the need for fa...

Energy efficient architecture research has flourished recently, in an attempt to address packaging and cooling concerns of current microprocessor designs, as well as battery life for mobile computers. Moreover, architects have become increasingly concerned with the complexity of their designs in the face of scalability, verification, and manufacturing concerns. In this paper, we propose and eva...

In this paper, we develop an efficient architecture for video scaling based on the adaptive image scaling algorithm [3] ,[4]. We then develop the design of the computation units and perform synthesis to show that the chip area required to perform scaling from QCIF to 4CIF is about 20mm2 using 0 . 5 ~ technology. In video applications, the data rate involved is extremely high. When the available...

The Viterbi algorithm (VA) is characterized by a graph, called a trellis, which defines the transitions between states. To define an area efficient architecture for the VA is equivalent to obtaining an efficient mapping of the trellis. In this paper, we present a methodology that permits the efficient hardware mapping of the VA onto a processor network of arbitrary size. This formal model is em...

One key technique for improving the coding efficiency of H.264 video standard is the entropy coder, contextadaptive binary arithmetic coder (CABAC). However the complexity of the encoding process of CABAC is significantly higher than the table driven entropy encoding schemes such as the Huffman coding. CABAC is also bit serial and its multi-bit parallelization is extremely difficult. For a high...

Content addressable memory (CAM) is a type of solid-state memory in which data is provided as input and an operation is performed to returns the address as output. Unlike other memories (SRAM, DRAM), it performs the search operation in parallel on complete location at once, offered significant reduction in searching time. A ternary content addressable memory (TCAM) is a specialized CAM design f...

Image processing operations can be divided into two classes, those pre-processing operations that are marketand application-spe­ cific, and those widely-used operations that are useful in any applica­ tion that requires the display of two-dimensional images. In the inter­ est of achieving real-time rates for the broader class of 2-D image display operations, Hewlett-Packard has developed a hard...

The Cadence Tensilica ConnX DSP family based on the Xtensa® customizable processor is specifically designed for wireless communication modem (PHY layer 1) systems. Cadence has worked closely with customers and software PHY companies that create wireless communication algorithms to drive product development. The Xtensa customizable processor gives modem developers a powerful starting point for s...

Data center network (DCN) architecture is regarded as one of the most important determinants of network performance. As the most typical representatives of DCN architecture designs, the server-centric scheme stands out due to its good performance in various aspects. In this paper, we firstly present the design, implementation and evaluation of SprintNet, a novel server-centric network architect...